mt90226ag ETC-unknow, mt90226ag Datasheet - Page 5

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

MT90225/226
Data Sheet
List of Figures
Figure 1 - MT90225/226 Functional Block Diagram ................................................................................................1
Figure 2 - MT90226 Pinout (Bottom View) ..............................................................................................................9
Figure 3 - MT90225 Pinout (Bottom View) ........................................................................................................... 10
Figure 4 - MT90225/226 Functional Block Diagram -Transmitter ........................................................................ 24
Figure 5 - Example of TC Mode Operation (Using Four of Sixteen Possible UTOPIA-Output Ports) .................. 26
Figure 6 - Cell Delineation State Diagram ............................................................................................................ 26
Figure 7 - SYNC State Block Diagram ................................................................................................................. 27
Figure 8 - Single mode - Generic 1.544 MHz ....................................................................................................... 29
Figure 9 - Single mode - Generic 2.048 MHz ....................................................................................................... 30
Figure 10 - Single mode - ST-BUS....................................................................................................................... 31
Figure 11 - TXCK and TXSYNC Output Pin Source Options ............................................................................... 37
Figure 12 - ATM Interface to MT90225/226 ......................................................................................................... 41
Figure 13 - ATM Interface to Multiple MT90225/226 ............................................................................................ 42
Figure 14 - IRQ Register Hierarchy ...................................................................................................................... 44
Figure 15 - MT90225 interfacing MT9076 ST-BUS mode with all links synchronous. ......................................... 67
Figure 16 - MT90225 interfacing MT9076 ST-BUS mode with asynchronous links. ............................................ 68
Figure 17 - MT90225 interfacing MT9076 Generic mode with asynchronous links. ............................................ 69
Figure 18 - MT90225 interfacing MT9072 ............................................................................................................ 70
Figure 19 - Setup and Hold Time Definition ......................................................................................................... 75
Figure 20 - Tri-State Timing ................................................................................................................................. 75
Figure 21 - Output Delay Timing .......................................................................................................................... 75
Figure 22 - CPU Interface Motorola Timing - Read Access ................................................................................. 77
Figure 23 - CPU Interface Intel Timing - Read Access ........................................................................................ 78
Figure 24 - CPU Interface Motorola Timing - Write Access ................................................................................. 79
Figure 25 - CPU Interface Intel Timing - Write Access......................................................................................... 80
Figure 26 - ST-BUS Timing .................................................................................................................................. 82
Figure 27 - Generic Bus Timing ........................................................................................................................... 83
Figure 28 - JTAG Port Timing .............................................................................................................................. 84
Figure 29 - System Clock and Reset.................................................................................................................... 85
Zarlink Semiconductor Inc.
v