mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 106

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Sub-modes of Operation (PLL_MODE_SEL bits)
Within each mode described above, the PLL has four sub-modes:
•
•
•
•
More detail regarding how to configure the PLL for the various modes of operation can be found in the register
descriptions for the Clock Management Module, found in Section 6.2.8 on page 149.
Frequency Behaviour
The PLL must generate frequencies with an accuracy as stated in Table 21. The accuracy defines the freerun
accuracy and the locking range of the PLL. The accuracy of the master clock (MCLK), which has to be running at
66 MHz, must be incorporated into these figures. A freerun accuracy of approximately 0.1 ppm and a locking range
of approximately 250 ppm has been implemented, thereby allowing 100 ppm MCLK accuracy and a 150 ppm input
clock / RTS nibble range.
Jitter and Wander
The af-vtoa-0078.000 standard with respect to jitter and wander points to several ANSI and ITU-T standards, as
summarized in Table 22. The jitter requirements are met in all clocking modes. The wander requirements may not
(nor need they) be met in adaptive mode.
The standards from Table 22 specify wander/jitter input tolerance and maximum output jitter. For the input wander/
jitter tolerance, the low frequency parts are the largest and are therefore the most important for the PLL
requirements (see Table 23). With a corner frequency larger than 1.2 Hz, the PLL will follow wander below 0.1 Hz.
Normal sub-mode: The input (be it a clock, RTS nibbles, or phasewords) is used to synchronize the PLL
output clock to the input.
Holdover sub-mode: Either when configured as such by the user (via the PLL_MODE_SEL bits) or when a
port experiences an LOS condition (while operating in UDT mode), the PLL is switched to holdover sub-
mode. When in the holdover state, the PLL ignores the input and holds the output clock at its current
deviation from the center frequency.
Freerun sub-mode: In this sub-mode, a clock rate of 1.544 MHz, 2.048 MHz, or 4.096 MHz is generated. No
input is used and the output frequency is fixed to the nominal center frequency.
CPU sub-mode: In this mode of operation, the offset from the center frequency of the output clocks is
determined by the value written to the per-port Clocking DCO Difference Register by an external CPU. The
value programmed by the CPU is used to set the PLL output frequency directly, instead of using the PLL’s
internal filter output. This mode is intended to put an external CPU into the PLL loop. The CPU can read the
filter output (from the per-port Clocking Phase Accumulator Register), process it, and write the desired factor
to the DCO. This mode of operation might be used if the user wanted to implement a loop filter with a very
large time constant.
C1M5 (DS1)
C2M (E1)
Clock
C4M
C1M5 (DS1)
C2M (E1)
Table 21 - Center Frequency and Accuracy
Clock
Frequency (MHz)
Table 22 - Relevant Specifications
1.544
2.048
4.096
Zarlink Semiconductor Inc.
MT90528
ANSI T1.102
ITU-T G.824
ITU-T G.823
Jitter
106
Accuracy (ppm)
-0.13
0.05
0.05
ANSI T1.403
ITU-T G.824
ITU-T G.823
Wander
1 UI (ns)
648
488
244
Data Sheet