mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 187

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

8.2
End-to-end latency, or delay, of the AAL1 segmentation and reassembly process of the MT90528 can be expressed
in a simplified manner as:
Some components of the latency, such as UDT cell payload assembly delay, are determined by the AAL1
standards. Some components of the latency are partially under the control of the application, such as SDT cell
payload assembly time where the number of channels can be increased to reduce cell payload assembly time.
Some components of the latency are a function of the MT90528 architecture, which has been designed to minimize
this latency. Finally, some components are externally determined, such as the physical layer and network delays,
and network Cell Delay Variation (CDV) which must be compensated for in the CDV buffering.
NOTE: “N” is the number of TDM channels carried by a particular ATM VC.
Cell Payload Assembly delay is the amount of time the TDM interface requires to deliver enough data to fill an AAL1
cell. Note that the latency given in Table 108 is for the first bit of TDM data packed in the AAL1 cell, i.e. the bit which
sees the longest delay before cell transmission. Since reassembly latency is inverted from this segmentation
latency (first-in-first-out) this method gives correct end-to-end latency for all bits in the cell when segmentation and
re-assembly delays are summed. The cell payload asssembly delay in SDT mode is a function of “N”, the number of
TDM channels carried by the VC. The FLOOR[x] function means “the largest integer less than, or equal to, x” and
the CEIL[x] function means “the smallest integer greater than, or equal to, x”. Cell payload assembly is a static
delay in UDT mode. Cell payload assembly is a variable delay in SDT mode, due both to the variation in payload
size (46 bytes and 47 bytes) specified in the AAL1 standards, and to remainders when fitting N channels into the
cell payload.
TX Queuing represents the possible delay due to cell operations queuing in front of the single high-speed TDM
segmentation and cell-assembly engine (TX_SAR). In UDT mode, worst case for this is the time taken to process
27 cells (one for each of the other TDM ports). In SDT mode, worst case for TX Queueing with a porperly
configured control structure is always less than a TDM frame (125 microseconds). This is a variable delay, and the
number given here is the peak, worst-case, low-probability value.
TX Processing is the time required for internal processing and data moves. This is a fixed delay in UDT and SDT
mode.
Mode
UDT T1
UDT E1
SDT
SDT Trunking
N > 46
Segmentation and Reassembly Latency
end-to-end delay =
cell payload assembly time + internal TX queuing + internal TX processing
+ physical layer and network delays
+ UTOPIA RX queuing + internal RX processing + pointer offset + CDV buffering
Cell Payload Assembly
(Psec)
243.5
183.6
min: FLOOR[46/N] X 125
max: CEIL[47/N] X 125
125
Table 108 - Segmentation Latency
Zarlink Semiconductor Inc.
TX Queuing
(Psec)
min: 0
max: 62.9
min: 0
max: 62.9
min: 0
max: 125
min: 0
max: 125
MT90528
187
TX
Processing
(Psec)
2.3
2.3
125
125
Total TX / Segmentation
(Psec)
min: 245.8
max: 308.7
min: 185.9
max: 248.8
min: 125 + FLOOR[46/N] X 125
max: 250 + CEIL[47/N] X 125
min: 250
max: 375
Data Sheet