mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 93

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.7.2
4.7.2.1
This sub-module acts as the interface between the Clock Management module and the TDM Interface module.
STiCLK_p signals received at the TDM interface are input to this sub-module and are directed to other portions of
the Clock Management module. In the output direction, SToCLK_p, C4M/C2M, and framing signals are generated
by this sub-module for output to the TDM Interface module. The user has full programmability to select the source
of the output clock for each TDM port.
A single interface is used to communicate with the TDM Interface module when using either UDT or SDT
formatting. A separate interface and additional clocking circuitry are provided for operation in TDM backplane
mode. Both interfaces and the associated circuitry are shown in Figure 34 on page 95 and are explained more fully
in the text which follows.
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Note: “_p” notation indicates per-port implementation.
Functional Description
RX_SAR or
Interface to TDM Sub-Module
RX_SAR
TX_SAR
Module
Module
UDT
SDT
Figure 33 - High-Level Block Diagram of the Clock Management Module
Received RTS
Handshaking
(Receive RTS)
Adaptive Clock
Recovery
Handshaking
Generated RTS
Handshaking
(Transmit RTS)
CLOCK RECOVERY
SUB-MODULE
Zarlink Semiconductor Inc.
MT90528
CLOCK MANAGEMENT
93
MODULE
CLOCK CONTROL
LOS_p
STiCLK_p
SToCLK_p
F0
C4M/C2M
SUB-MODULE
MT90528 Device
TDM Bus
Module
Clock
Logic
Data Sheet
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