mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 99

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

A secondary function of the network clock divider circuit is the generation of an internal 8 kHz clock signal from the
19.44 MHz network clock. This 8 kHz signal can then be used as a reference clock to the internal PLLs outlined in
Section 4.7.2.7. As an alternative, if the user wishes to provide his own 8 kHz reference for the internal PLL, an 8
kHz signal can be input directly on the PHY_CLK pin, provided that SRTS clock generation/recovery will not be
used.
4.7.2.4
In the segmentation direction, the purpose of the transmit SRTS circuit sub-module is to generate 4-bit Residual
Time Stamps (RTSs) to be inserted within the headers of ATM cells output on the UTOPIA bus. In the reassembly
direction, this circuit is used to generate local RTS values which are compared (by an internal PLL) with the RTS
values extracted from received cells. Segmentation operation is explained in this section, but the reassembly
function is discussed in Section 4.7.2.5, “Receive SRTS Circuit Sub-Module”.
As outlined in U.S. Patent No. 5,260,978, in the segmentation direction, the transmit SRTS circuit compares the
local clock rate, determined by STiCLK for a particular port (in independent clocking or ST-BUS backplane mode) or
PHY_CLK (8
kHz or 19.44
Transmit SRTS Circuit Sub-module
MHz)
PHY_CLK
/ 2430
Figure 38 - Network Clock Dividers
/ 8 (DS1/E1)
Zarlink Semiconductor Inc.
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/ 128
/ 64
/ 32
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MT90528
8_KHZ_SEL
Mux
2:1
99
75,937.5 Hz
151,875 Hz
303,750 Hz
607,500 Hz
1.215 MHz
2.430 MHz
Clock Management Module
8000 Hz
FNXI2_RATE<2:0>
FNXI1_RATE<2:0>
Mux
Mux
To internal
digital PLL
8_kHz
fnxi1
fnxi2
Data Sheet