mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 189

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Since the variable portions of the delay in segmentation and reassembly effectively become part of the CDV that
must be compensated for in the CDV buffer, we can omit them from the end-to-end calculation. (Also remembering
that the variable delays given in Table 108 and Table 109 are worst-case numbers that will never be experienced by
most applications.) The delay variation in SDT mode due to payload size variation and divide-by-N remainders is
also part of the CDV compensated for by the CDV buffer, but is left in here to illustrate the effects on delay of the
value of N.
The Max_Lead values should be set by the user in accordance with the expected or negotiated CDV, as explained
in “UDT Mode of Operation” on page 79 and in “SDT Mode of Operation” on page 80. These recommended settings
are used to evaluate Max_Lead in Table 110. It can be seen that the difference between the minimum and
maximum static delay in each mode is due largely to the pointer offset, which, as described earlier, is the random
offset between the time of the segmentation operation and the time of the reassembly operation.
The delay values for SDT assume no TDM switching delay. This means that the given delay is for a TDM byte
which is driven out at the RX end on the same TDM channel number as it was sampled in at the TX end. For
example, if the TDM byte comes into the segmentation end on TDM channel 3, it is driven out at the reassembly
end on TDM channel 3.
Mode
SDT Trunking -
UDT E1 - min
UDT T1 - min
SDT - min
max
max
max
max
min
Total Static TX /
Segmentation
(Psec)
245.8
245.8
185.9
185.9
125 + FLOOR[46/N] X 125
125 + CEIL[47/N] X 125
250
250
Table 110 - End-to-End Latency
Zarlink Semiconductor Inc.
MT90528
Total Static RX /
Reassembly
(Psec)
1.7 + 2.59 X Max_Lead
245.2 + 2.59 X Max_Lead
1.7 + 1.95 X Max_Lead
185.3 + 1.95 X Max_Lead
125 + 62.5 X Max_Lead
250 + 62.5 X Max_Lead
125 + 62.5 X Max_Lead
250 + 62.5 X Max_Lead
189
End-to-End Latency
(Psec)
490.96 + CDV + network
734.46 + CDV + network
370.9 + CDV + network
554.5 + CDV + network
375 + FLOOR[46/N] X
125 + CDV + network
500 + CEIL[47/N] X 125 +
CDV + network
500 + CDV + network
625 + CDV + network
Data Sheet