mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 97

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

MT90528
Data Sheet
MT90528
TDM_CLK
To “Interface to
TDM_CLK
(Synchronous Clock
From external PLL
TDM Sub-Module”
#2)
Multiplexer
Clock Rates: 1.544 MHz (DS1); 2.048 MHz
Clock Management Module
(E1 and framed DS1); 4.096 MHz (ST-BUS)
Figure 36 - Synchronous TDM-Rate Clock Generated by External PLL
Although the simple process outlined above provides synchronous clocking, the MT90528 also provides circuitry
internal to the device which allows the use of plesiochronous clock recovery methods. Using the circuitry shown in
Figure 37, the user is able to select a signal to provide a reference clock for the external PLL. The sources available
are the per-port STiCLK inputs and the PLLCLK signals which are generated or recovered for each DS1/E1 port of
the MT90528.
The user can select the STiCLK input or the internal PLL clock from any DS1/E1 port to serve as a reference signal
for the generation of SToCLK for any other port. The user is able to choose any of the 56 (2 * 28 ports) sources for
the primary reference (PRI_REF), and any of the 56 sources as the secondary reference (SEC_REF). PRI_LOS
and SEC_LOS are set to their selected port’s LOS. The user selection for PRI_REF is overridden in an LOS
condition to always provide the corresponding port’s internal PLL clock as the primary reference. The user selection
for SEC_REF is not overridden by an LOS condition.
It is up to the user to select mutually-exclusive sources for the external PLL if redundancy is the goal. Regardless of
whether the primary or secondary reference is used, the external PLL output must be programmed to match the
desired line rate. The line rate signal which is output from the external PLL is input to the MT90528 device at the
TDM_CLK input pin. Alternatively, if the user does not wish to use an external PLL, the PRI_REF signal can be
routed directly to the “common clock” multiplexer described previously. This implementation was shown in
Figure 34.
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Zarlink Semiconductor Inc.