mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 69

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

SDT Reassembly Control Structures
Within the SDT RX_SAR, there is an internal memory which is 16 Kwords long and 16 bits wide, to permit the setup
of VCs of varying size and configuration. The MT90528 can handle up to 896 single-channel VCs (a full E1 of 32
channels on each of the 28 ports). Such a configuration uses the maximum internal memory resources (maximum
overhead is required for each “n=1” VC). However, many other configurations with different “n” are also permissible.
Unlike the control structures in UDT mode, SDT Reassembly Control Structures do not have as many restrictions
on their location. Although all of the SDT control structures must start on 32-byte (16-word) boundaries, the
boundary which is selected for each control structure does not matter (e.g., the control structure for a VC on port 5
may be physically located in memory at an earlier location than the control structure for a VC on port 0). As well, it
is possible for a VC to be carrying data which is destined for multiple TDM ports (e.g., Channel 0 of the VC may be
destined for port 0, but channel 1 might be destined for port 27). The TDM port destination of the data is ultimately
determined by the programming of the TDM SDT Reassembly Control Structure (see Figure 13 on page 46). It is
important to note that the location of the SDT Reassembly Control Structure in internal memory must be correlated
with the Reassembly Control Structure Address within the UTOPIA’s look-up table entry for the particular VC.
When a VC is configured as basic SDT, the control structure uses from 30 bytes to 284 bytes, depending on the
number of channels carried by the VC (up to 128). The various fields of the SDT Reassembly Control Structure are
shown in Figure 28 and explained in Table .
For debug and statistics-gathering purposes, the CPU can read the SDT Reassembly Control Structure contents,
one word at a time.
Byte
Add
+0C
+00
+02
+04
+06
+08
+0A
+0E
+10
+12
+14
+16
Note 1: Fields which appear in dark grey are reserved fields
which must be cleared by software upon initialization.
Note 2: Fields which appear in grey are those which are
updated by hardware.
Note 3: UDT Reassembly Control Structures must always
start on 16-word (32-byte) boundaries.
15
V_RTS
V
<3:1>
Res
Res
14
Misinserted Cells
AAL1 Sequence
Buffer Overflows
Res
Reserved
13
Reserved
Reserved
Errors
12
<3:1>
RTS
Reserved
11
10
UDT RX_SAR Write Pointer
Reassembled Cells
TDM Read Pointer Plus
9
Last
Seq
8
Average
Maximum Lead
7
R
o
AAL1 Header Errors
6
A S
Buffer Underruns
R
o
Good
Last
R
5
o
Lost Cells
Late Cells
Figure 27 - Reassembly Control Structure - UDT Format
R
4
o
I
VC TDM
Fast State
C
3
R
o
Port
PV_SN
R
o
2
<2:0>
R
1
o
0
R
o
Word
Add
+0A
+0B
+00
+01
+02
+03
+04
+05
+06
+07
+08
+09
Zarlink Semiconductor Inc.
MT90528
A (Adaptive Enable): If set, the fill-level of the UDT Reassembly Circular Buffer associ-
ated with this VC is used to provide adaptive clocking information for the TDM port.
S (SRTS Enable): If set, this VC is carrying RTS clocking information for the TDM port.
VC TDM Port: Identifies the TDM port (0 to 27) with which this VC is associated. Must
correspond to the location of this control structure within the internal memory.
Maximum Lead: Maximum allowable distance between the TDM Read Pointer and the
UDT RX_SAR Write Pointer within the UDT Reassembly Circular Buffer.
V_RTS<3:1> (RTS Validity): Bits indicating whether the individual bits in RTS<3:1> are
valid and can therefore be used by the PLL for clock recovery processing.
RTS<3:1>: Intermediate RTS value used by the clock recovery circuit.
Last Seq (Last Sequence Number): This state variable keeps track of the last sequence
number received by the Fast SN Processing state machine.
Last Good (Last Good Sequence Number): This state variable keeps track of the last
valid or in-sequence sequence number received by the Fast SN Processing SM.
Fast State: Indicates which state the Fast Sequence Number Processing SM will enter
upon the arrival of the next cell from this VC.
I (Initialized): ‘0’ = VC uninitialized; ‘1’ = VC initialized. Must be initialized to ‘0’ by soft-
ware.
C (Next CD State): Indicates which state the Correction/Detection SM will enter upon the
arrival of the next cell from this VC. Must be initialized to’0’ (Correction).
PV_SN<2:0> (Previous Valid Sequence Number): Sequence number of the last valid,
in-sync cell received by the SRTS circuitry.
UDT RX_SAR Write Pointer: Indicates which location will next be written to within the
UDT Reassembly Circular Buffer in internal memory.
TDM Read Pointer Plus Average: This read-only field contains the value of the TDM
Read Pointer plus average lead. Unless an underrun has been reported, this field is
cleared to zero.
MIB Statistics: AAL1 Sequence Errors, AAL1 Header Errors, Misinserted Cells, Lost
Cells, Buffer Overflows, Buffer Underruns, and Late Cells are 8-bit fields for each MIB
statistic which must be collected on a per-VC basis. Reassembled Cells is stored in a
16-bit field.
V (VC Arrival): This bit is set by the UDT RX_SAR each time a cell arrives on this VC.
The CPU can clear it to ‘0’ to provide per-VC timeout monitoring.
Ro: Status bits which indicate rollovers on MIB status fields. The eight rollover bits corre-
spond to the order of the MIB statistics fields in the control structure: bit<0> = Reassem-
bled Cell Rollover, bit<1> = AAL1 Header Errors Rollover, etc.
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Data Sheet