mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 180
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mt90528ag2
Manufacturer Part Number
mt90528ag2
Description
28-port Primary Rate Circuit Emulation Aal1 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90528AG2.pdf
(195 pages)
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7.2.3.3
This section contains the timing diagrams for the MT90528 setup in UTOPIA Level 2 as a PHY device. For
functional timing diagrams, refer to the ATM Forum Level 2 specification (af-phy-0039.000).
Since the MT90528 does not support multi-PHY (MPHY) operation in ATM mode, the Level 2 ATM timing diagrams
are identical to the ones for Level 1 operation, except that in Level 2, the MT90528 features a 16-bit data bus in
both the TX and RX directions and it supports up to 80pF of load at 33 MHz and 40 pF at 52 MHz. Note that the
address bus is only used when in PHY mode.
UTO_IN_CLK Period
UTO_IN_CLK Pulse Width (HIGH / LOW)
Input Setup Time -
(UTO_IN_CLAVATM_ENBPHY, UTO_IN_SOC
asserted and UTO_IN_DATA[15:0],
UTO_IN_ADDR[4:0] VALID) to UTO_IN_CLK
rising
Input Hold Time - UTO_IN_CLK rising to
(UTO_IN_DATA[15:0], UTO_IN_ADDR[4:0]
INVALID and UTO_IN_SOC,
UTO_IN_CLAVATM_ENBPHY de-asserted)
Output Delay - UTO_IN_CLK rising to
UTO_IN_ENBATM_CLAVPHY asserted
Output Hold Time - UTO_IN_CLK rising to
(UTO_IN_ENBATM_CLAVPHY change)
Drive to High-Z - UTO_IN_CLK rising to
UTO_IN_ENBATM_CLAVPHY HIGH-Z
High-Z to Drive - UTO_IN_CLK rising and
UTO_IN_ENBATM_CLAVPHY HIGH-Z to
UTO_IN_ENBATM_CLAVPHY change
Table 105 - UTOPIA Level 2 Interface Timing - PHY mode - Incoming Data (UTOPIA TX Bus)
UTOPIA Level 2
Characteristic
t
UTX2H/L
t
t
t
t
t
Sym.
t
t
UTXDZ
UTXZX
UTX2P
UTXIS
UTXIH
UTXD
UTXH
Zarlink Semiconductor Inc.
MT90528
19.23
Min.
7.7
4
1
1
1
1
1
1
1
180
t
UTX2P
Typ.
/2
Max.
13.8
20.5
17.5
28.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTO_IN_CLK = 52 MHz
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
=40 pF; UTO_IN_CLK < 52 MHz
=80 pF; UTO_IN_CLK < 33 MHz
=40 pF; UTO_IN_CLK < 52 MHz
=80 pF; UTO_IN_CLK < 33 MHz
=40 pF; UTO_IN_CLK < 52 MHz
=80 pF; UTO_IN_CLK < 33 MHz
=40 pF; UTO_IN_CLK < 52 MHz
=80 pF; UTO_IN_CLK < 33 MHz
Test Conditions
Data Sheet
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