mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 20

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

3.0
3.1
Ball pin numbers are given in the following tables as defined in Figure 4 on page 33. Pins for buses are listed with
the MSB appearing first.
I/O definitions are: Output (O), Input (I), Bidirectional (I/O), Power (PWR), or Ground (GND).
Input pad types are: CMOS or Schmitt, 3.3 V. The notations “PU” and “PD” are used, respectively, to indicate that a
pad has a weak internal pullup or pulldown resistor. All 3.3 V inputs are 5 V tolerant. The 3.3 V CMOS inputs have
a switching threshold of 1.6 V, and tolerate input levels of up to 5 V; therefore they are 5 V TTL compatible.
Output pad types are described by voltage rail and current capability. 3.3 V CMOS outputs will satisfy 5 V TTL input
thresholds at the rated current of the output.
D10, C9, B9, A9,
D9, C8, B8, A8,
C15, A16, E15,
D15, B16, C16,
A17, B17, D16,
C17, A18, B18,
C18, D17, A19,
B19, C19, D18,
D11, E11, C10,
B10, A10, C11,
Ball Pin #
B11, D12
A20, E17
Functional Pin Descriptions
Pin Descriptions
C12
A11
D8
C7
E9
A7
B7
CPU_DATA[15:0]
CPU_ADD[20:1]
RDY/DTACK
Pin Name
Intel/Moto
WR/R_W
RD/DS
AEM
IRQ
CS
Table 1 - Microprocessor Interface Pins
I/O
I/O
O
O
I
I
I
I
I
I
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V, 24mA Ready (Intel) / Data Transfer Acknowledge (Motorola). Acts as
3.3 V, 24mA Active LOW interrupt line (operates as open-drain: high-imped-
PD / 12mA
Type
Zarlink Semiconductor Inc.
PD
PU
PU
PU
PD
PD
MT90528
This input selects the microprocessor interface mode as Intel
(pulled HIGH) or Motorola (pulled LOW). This pin must be config-
ured before power-up.
Active LOW chip select signal.
Active LOW Write Strobe (Intel) / Read_Write (Motorola).
Active LOW Read Strobe (Intel) / Active LOW Data Strobe
(Motorola).
Access External Memory - CPU accesses external memory
when HIGH (internal memory and registers when LOW). This pin
is usually connected to a high-order CPU address line.
CPU Address lines A20-A1.
All microprocessor accesses to the device are word-wide, but
addresses in this document are given as byte addresses. The
virtual A[0] bit would select between high and low bytes within a
word.
CPU data bus. All CPU accesses are word accesses.
normal output in Intel mode, tristated when CS is HIGH; acts as
active LOW pseudo-open-drain output in Motorola mode.
ance when inactive).
20
Description
Data Sheet