mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 56

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Depending on the value of the DS field of a look-up table entry, the UTOPIA module can process the cell in one of
the following ways:
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Refer to Figure 18 on page 57 for an overview of the complete UDT VCI/VPI comparison and look-up table
searches.
RX Parity
The RX Parity sub-module’s role is to calculate the odd parity bit over UTO_IN_DATA[15:0] (over
UTO_IN_DATA[7:0] when operating in 8-bit mode). The module then compares the internally calculated value with
the one supplied by the external system on UTO_IN_PAR. If the parity bits do not match, a counter is incremented
in the UTOPIA Parity Mismatches Register (400Eh).
if DS = “00”, and the global UKSEL bit is set (in the UTOPIA Configuration Register), the cell is sent to the
Data RX_SAR for eventual storage in the Receive Data Cell Buffer in external memory
if DS = “00”, and the global UKSEL bit is cleared, the cell is discarded and the UTOPIA module simply starts
processing the next cell
if DS = “01”, the cell as well as the SDT Reassembly Control Structure Address from the look-up table entry
are sent to the SDT RX_SAR
if DS = “10”, the complete cell is sent to the Data RX_SAR. F4 level OAM cells (cells with VCI = 3 or VCI = 4)
should be set to DS = “10”
if DS = “11”, the cell is discarded and the UTOPIA module simply starts processing the next cell.
Zarlink Semiconductor Inc.
MT90528
56
Data Sheet