mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 94

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Operation of SDT/UDT Interface
There are 4 possible user-selectable clock sources for SToCLK:
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The user is able to select the desired clock source via the CLKSEL bits (found in the per-port Clocking
Configuration Register at 5200h + p*10h), with MCLK/2 being the default clock which is output on SToCLK. In the
event of an LOS condition, the multiplexer automatically selects the port’s PLLCLK reference to be output on
SToCLK, if the user had originally selected to use STiCLK as the source of SToCLK. In this way, even if the port’s
TDM input clock signal fails, the SToCLK signal is still valid. (Note: The port’s internal PLL goes into holdover mode
upon receiving the LOS indication.)
The user selects (via register bits) what type of clock is generated by the internal PLL. This clock may have one of
the following possible sources:
More information about the PLL implementation can be found in Section 4.7.2.7, “Internal Digital PLL Sub-Module,”
on page 104.
Operation in TDM Backplane Mode
When operating in TDM backplane mode, there are two signals which are exchanged between the backplane and
the MT90528 device: F0 and C4M/C2M. These bidirectional signals (inputs when the MT90528 is slaved to the
backplane; outputs when the MT90528 is the backplane master) are generated only once per device. Unlike the
per-port clock and framing signals, these signals are directed into the Clock Management module from the external
pins. These signals are then transferred to the TDM bus module.
If the MT90528 is operating in slave mode, the C4M/C2M signal is routed to the TDM bus module, where it is used
as both the sample and drive clock for each of the DS1/E1 ports. The F0 signal from the external pin is transmitted,
unchanged, to the TDM bus module.
When operating in master mode, the Clock Management module generates both the C4M/C2M signal and the F0
signal. These signals are transmitted to external device pins as well as to the TDM bus module. The C4M/C2M
signal is generated from a common TDM line rate clock, as explained in Section below. The internal frame pulse
signal, F0, is generated as a divided-down version of the C4M/C2M clock. The frame pulse signal is configured to a
user-programmable format (either an ST-BUS or Generic frame pulse) prior to being output to both the TDM bus
module and the F0 pin.
Common Clock Source Generation
An additional function of the circuitry shown in Figure 34 is the generation of a common TDM line rate clock for use
by all of the DS1/E1 ports of the MT90528 device when it is not in backplane mode. The user is able to select the
source for this signal (labelled as common TDM rate clock in Figure 34) as coming from either an internal or an
external reference. If an external reference is selected, the common clock is sourced from the TDM_CLK pin. On
the other hand, should the user not want to employ an external PLL, an internal reference may be selected. In this
case, the common clock comes from the PRI_REF reference signal. The PRI_REF signal, which is explained in
the STiCLK signal for the port
the clock generated by the port’s internal digital PLL and transmitted via PLLCLK
a synchronous clock generated from one of a number of user-selectable sources. This is a common clock
which is available to all of the DS1/E1 ports of the MT90528.
a divided-down version of the system clock (MCLK/2).
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a synchronous clock generated using the port’s STiCLK input reference (in Line Clocking mode)
a synchronous clock generated using a network reference (in Network mode)
the SRTS-recovered clock for the port (in SRTS mode)
the clock generated using Adaptive Clock Recovery methods for the port (in Adaptive mode).
Zarlink Semiconductor Inc.
MT90528
94
Data Sheet