mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 109

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

5.0
5.1
5.2
Several buffers and structures are stored in external memory when transmitting and receiving SDT and/or data
cells. Since the location of the buffers and structures is not hard-coded in the hardware, the user can program the
chip to put these at any location in the external memory. The following list describes the various items located in
external memory, if the chip is programmed to support data and SDT cells. Note that the entire external memory
space is used (1M word) if the maximum size is chosen for all of these items.
As pointed out previously in this document, note that no external memory is required if the device is configured
solely for UDT operation, provided that no data cell transmission or reception is required.
•
8 xxxx - TX_SAR Control Memory
9 xxxx - SDT RX_SAR Control Memory
A xxxx - TDM Output Control
B xxxx - UDT RX_SAR Control Memory
C xxxx - UTOPIA
UTOPIA Look-up Table
•
•
CPU Byte Address
80000 - 87FFE
90000 - 97FFE
A0000 - A003E
A0800 - A083E
...
AD800- AD83E
BE000 - BE01E
BE020 - BE03E
...
BE360 - BE37E
C 0000 - C07FE
C 1000 - C11FE
Internal Memory Map
External Memory
configured based on N, the number of least-significant VCI bits, and M, the number of least-significant
VPI bits, (programmed by the user in the UNCB register) used to form the search addresses within the
look-up table
maximum of 64 K words
Memory
(hex)
Per-VC UDT and SDT Segmentation Con-
trol Structures
Segmentation SDT Pointer Tables
Per-VC SDT Reassembly Control Struc-
tures
TDM SDT Reassembly CS - port #0
TDM SDT Reassembly CS - port #1
...
TDM SDT Reassembly CS - port #27
UDT RX_SAR CS - port #0
UDT RX_SAR CS - port #1
...
UDT RX_SAR CS - port #27
UTOPIA RX FIFO
UTOPIA TX FIFO
Table 25 - Internal Memory Map
Description
Zarlink Semiconductor Inc.
MT90528
109
Normal CPU access - writes and reads
Buffer is 16 Kwords long
Normal CPU access - writes and reads
Buffer is 16 Kwords long
Normal CPU access - writes and reads
Each per-port buffer is 32 words long.
Normal CPU access - writes and reads
Each per-port buffer is 16 words long.
CPU read access for debug
32 cells X 64 bytes/cell = 2048 bytes
CPU read access for debug
8 cells X 64 bytes/cell = 512 bytes
Notes
Data Sheet