mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 24

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

G2, H4, G3,
H3, J4, G1,
G4, F3, E1,
E2, F4, D1,
F1, F2, H5,
L4, J1, J2,
Ball Pin #
J3, K4
M4
H2
E3
H1
K5
K3
UTO_IN_ENBATM
UTO_IN_ADD[4:0]
UTO_IN_DATA[15
UTO_IN_CLAVAT
UTO_IN_SOC
UTO_IN_CLK
UTO_IN_PAR
M_ ENBPHY
_ CLAVPHY
Pin Name
:0]
I/O
I/O 3.3 V CMOS
O
I
I
I
I
I
3.3 V, 16 mA
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
PD / 24 mA
Table 4 - UTOPIA Bus Pins
Type
PD
PD
PD
PD
PD
Zarlink Semiconductor Inc.
MT90528
Synchronization clock for data transfer on UTO_IN_DATA. This
clock can be output from an internal divider (equal to MCLK/2) or
input from an external source. (RxClk when the MT90528 is in
ATM mode; TxClk when the MT90528 is in PHY mode.)
Multi-PHY address signals. These address inputs are used to poll
the MT90528 and to select the next MPHY device to receive data
on UTO_IN_DATA. These signals are driven from the ATM-end to
the PHY-end, and only used when the MT90528 is in PHY mode.
(Inactive when the MT90528 is in ATM mode; TxAddr when the
MT90528 is in PHY mode.)
16-bit UTOPIA input bus for cell-based data. When in 8-bit mode,
only bits [7:0] are active. (RxData[15:0] when the MT90528 is in
ATM mode; TxData[15:0] when in PHY mode.)
Odd parity bit over UTO_IN_DATA[15:0]. When in 8-bit mode, odd
parity bit over UTO_IN_DATA[7:0]. (RxPrty when the MT90528 is
in ATM mode; TxPrty when in PHY mode.)
Start of Cell for UTO_IN_DATA. Active HIGH input signal indicat-
ing the first word/byte of the cell being received. (RxSOC when
the MT90528 is in ATM mode; TxSOC when in PHY mode.)
Handshake input for UTO_IN_DATA.
When the MT90528 is in ATM mode, this input is RxClav, indicat-
ing that the PHY-end has a complete cell to transfer on
UTO_IN_DATA.
When the MT90528 is in PHY mode, this input is TxEnb*, indicat-
ing that the ATM-end is transferring valid data on UTO_IN_DATA.
Handshake output for UTO_IN_DATA.
When the MT90528 is in ATM mode, this output is RxEnb*, indi-
cating that the MT90528 will begin to sample UTO_IN_DATA and
UTO_IN_SOC at the end of the next clock cycle.
When the MT90528 is in PHY mode, this output is TxClav, indi-
cating that the MT90528 can accept a complete cell on
UTO_IN_DATA.
24
Description
Data Sheet