mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 151

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Address: 5002 (Hex)
Label: PLLCS
Reset Value: 0000 (Hex)
SEC_SEL
Reserved
PRI_SEL
Label
Position
15:12
11:6
Bit
5:0
Table 76 - External PLL Clock Source Register
Type
R/W
R/W
R/O
Primary Clock Source for External PLL.
Used to select the primary clock source for the external PLL (signals output on PRI_REF
and PRI_LOS).
Bits<4:0> indicate which port should provide the clock source (only “00000”:“11011”
are valid choices).
Bit<5> indicates whether the port’s TDM input clock (STiCLK) or the port’s internally-gener-
ated PLL clock should be used as the clock source. ‘0’ = STiCLK; ‘1’ = PLLCLK.
Note: If the port selected to provide the primary reference experiences an LOS condition,
that port’s PLLCLK will be used as PRI_REF, even if the port’s STiCLK is selected via
PRI_SEL<5>.
Secondary Clock Source for External PLL.
Used to select the secondary clock source for the external PLL (signals output on
SEC_REF and SEC_LOS).
Bits<4:0> indicate which port should provide the clock source (only “00000”: “11011”
are valid choices).
Bit<5> indicates whether the port’s TDM input clock (STiCLK) or the port’s internally-gener-
ated PLL clock should be used as the clock source. ‘0’ = STiCLK; ‘1’ = PLLCLK.
Note: An LOS condition on the port selected to provide the secondary reference clock will
have no effect on the selection of the clock source for SEC_REF.
Always reads “0000”.
Zarlink Semiconductor Inc.
MT90528
151
Description
Data Sheet