mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 96

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.7.2.2
There are two possible options for generating a synchronous clock which is traceable to a Primary Reference
Source (PRS). The first option, referred to as Synchronous Clock #1, is generated via an internal digital PLL. The
second, Synchronous Clock #2, is provided via an external PLL. These options are available for UDT, SDT, and
TDM Backplane modes of operation.
Synchronous Clock #1 (Internal Digital PLL)
Each port within the MT90528 device has its own internal digital PLL. Refer to Section 4.7.2.7, “Internal Digital PLL
Sub-Module,” on page 104 for information regarding the specifics of the design and its operation. This PLL
performs various functions within the MT90528, including SRTS clock recovery (outlined in Section 4.7.2.5),
adaptive clock recovery (described in Section 4.7.2.6), and PRS-traceable clock generation, which is explained
here. Each PLL continuously generates a clock which runs at the TDM line rate.
In this mode, the reference clock for all of the PLLs is provided by an 8 kHz clock, derived as a divided-down
version of the network clock. The generation of this reference clock is explained in Section 4.7.2.3 on page 98. The
implementation of the synchronous clock generation is shown in Figure 35.
The clock output from the PLL (PLLCLK for each of the DS1/E1 ports) is transmitted to the port’s corresponding
SToCLK multiplexer.
Synchronous Clock #2 (External PLL)
As an alternative to the internal PLL, an external PLL may be used to provide a synchronous clock for transmission
onto the TDM output bus. Using this method, a PRS-traceable signal from an external PLL is input to the MT90528
via the TDM_CLK pin. Since this is a “common” clock signal (i.e., one per device), TDM_CLK is routed to a
multiplexer, as shown previously in Figure 34. The output of this multiplexer is a common clock which is routed to
the clock selection multiplexers (one per port) in the “Interface to TDM sub-module”, detailed previously in
Section 4.7.2.1. The implementation of the synchronous clock generation is shown in Figure 38.
Synchronous Clocking Circuit
Figure 35 - Synchronous Source Multiplied to TDM Bus Rate by Internal PLL
(generated by Network
Clock Divider Circuit)
8_kHz
Clock Management Module
Digital
PLL
Zarlink Semiconductor Inc.
MT90528
MT90528
96
(Synchronous Clock #1)
PLLCLK
TDM Sub-Module”
Clocking Circuit”
To “Interface to
Multiplexers &
“Synchronous
Multiplexers
Data Sheet