mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 76

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Note **: The per-port timeout circuitry for late-cell insertion is enabled only when the state machine is entering the
sync state. Therefore, late-cell insertion is only possible when the Fast SN Processing SM is in the “sync” state.
Here are some examples of incoming cell streams containing errors and the corresponding corrective actions taken
by the UDT RX_SAR.
Sequence number protection
failure (looks like single cell
loss)
NOTE: D indicates the insertion of a dummy cell containing user-programmable data.
single_cell_loss_
misinsertion
late_cell_insertion
Current State
Description of Error
Table 16 - Examples of Operation of the UDT Fast Sequence Number Processing State Machine
Table 15 - Operation of UDT Fast Sequence Number Processing State Machine
invalid sequence number
received cell is in sequence with last received
cell (i.e., single cell loss)
received cell is in sequence with last in-
sequence cell (i.e., cell misinsertion)
received cell has a valid sequence number
that is two greater than the last in-sequence
cell (i.e., sequence number protection failure)
received cell has valid sequence number, but
doesn’t meet any of the 3 previous criteria
invalid sequence number
received cell has a sequence number one
greater than the originally expected sequence
number (i.e., this appears to be a single-cell
loss)
received cell is that which was originally
expected (i.e., late cell arrival)
received cell has valid sequence number, but
doesn’t meet either of the 2 previous criteria
Transition Event
Sample Incoming Cell
1 - 3* - 3 - 4 - 5
Stream
Zarlink Semiconductor Inc.
MT90528
76
- discard cell
- accept received cell
- declare lost_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- discard cell (dummy cell already
inserted to take place of
misinserted cell)
- declare misinserted_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- discard received cell (extra
dummy cell was inserted when all
cells were actually received in
order)
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- discard cell
- discard cell
- accept received cell (dummy cell
was already inserted to replace the
lost cell)
- declare lost_cell_error
- declare aal1_seq_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- discard cell (because a dummy
cell was already inserted to replace
this one)
- declare late_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
- discard cell
- declare aal1_seq_error
Cells Used for
Reassembly
1 - D
Action Taken
2
- 3* - 4 - 5
1 AAL1 Sequence Error
start
sync
sync
sync
out_of_sync
start
sync
sync
out_of_sync
Errors Declared
Next State
Data Sheet
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Note