tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 112

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Microprocessor Interface
Microprocessor Interface Pinout Definitions
The Mode [1 and 3] specific pin definitions are given in Table 52. Note that the microprocessor interface uses the
same set of pins in all modes.
Table 52. Mode [1 and 3] Microprocessor Pin Definitions
1. INTERRUPT output is synchronous to the internal clock source RLCK-LIU. If RLCK_LIU is absent, the reference clock for interrupt timing
2. In the default (reset) mode, INTERRUPT is active-high. It can be made active-low by setting register GREG4 bit 6 to 1.
3. The DTACK output is asynchronous to MPCLK.
4. See Table 2. Pin Descriptions.
5. MPCLK is needed if RDY output is required to be synchronous to MPCLK.
Microprocessor Clock (MPCLK) Specifications
The microprocessor interface is designed to operate at clock speeds up to 16 MHz without requiring any wait-
states. Wait-states may be needed if higher microprocessor clock speeds are required. The microprocessor clock
(MPCLK, pin AE10) specification is shown in Table 53. This clock must be supplied only if the RDY (MODE 3) is
required to be synchronous to MPCLK.
Table 53. Microprocessor Input Clock Specifications
112
becomes an interval 2.048 MHz clock derived from the CHI clock.
Configuration
MPCLK
Name
Mode 1
Mode 3
Symbol
Number
Note 4
Note 4
Note 4
Note 4
AE10
AE10
t1
AD9
AD9
V24
U26
U23
U25
V26
V24
U26
U23
U25
V26
Pin
Period and
Tolerance
30 to 323
INTERRUPT
RDY_DTACK
INTERRUPT
RDY_DTACK
Device Pin
RD_R/W
RD_R/W
ALE_AS
ALE_AS
WR_DS
WR_DS
(continued)
MPCLK
MPCLK
A[11:0]
A[11:0]
Name
D[7:0]
D[7:0]
CS
CS
T
Typ
rise
2
INTERRUPT
INTERRUPT
Pin Name
Generic
DTACK
MPCLK
MPCLK
A[11:0]
A[11:0]
D[7:0]
D[7:0]
RDY
R/W
ALE
WR
DS
CS
RD
CS
AS
T
Typ
5
fall
2
3
1
1
Pin_Type
Min High
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
12
Duty Cycle
Active-High/
Active-High/
Active-High
Min Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Assertion
Sense
Low
12
Low
—
—
—
—
—
—
—
Preliminary Data Sheet
2
Lucent Technologies Inc.
Lucent Technologies Inc.
Unit
ns
Address Latch Enable
Microprocessor Clock
Microprocessor Clock
Data Acknowledge
R/W = 1 => Read
R/W = 0 => Write
Address Strobe
October 2000
Address Bus
Address Bus
Data Strobe
Chip Select
Chip Select
Read/Write
Function
Data Bus
Data Bus
Interrupt
Interrupt
Ready
Write
Read