tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 25

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Pin Information
Table 2. Pin Descriptions (continued)
Lucent Technologies Inc.
Lucent Technologies Inc.
† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
‡ Asserting this pin low will initially force RDY to a low state.
* I
u
indicates an internal pull-up, I
AD16
AB23
AD11
AA26
AF12
M26
AB4
R24
B23
A10
AA1
N24
A22
Y25
B21
AF9
U26
M3
E3
P3
C1
A8
C2
N1
Y4
C9
RCRCMFS [1 ]
RCRCMFS [2 ]
RCRCMFS [3 ]
RCRCMFS [4 ]
RCRCMFS [5 ]
RCRCMFS [6 ]
RCRCMFS [7 ]
RCRCMFS [8 ]
TCRCMFS [1 ]
TCRCMFS [2 ]
TCRCMFS [3 ]
TCRCMFS [4 ]
TCRCMFS [5 ]
TCRCMFS [6 ]
TCRCMFS [7 ]
TCRCMFS [8 ]
MPMODE
TSSFS [3 ]
TSSFS [4 ]
TSSFS [5 ]
TSSFS [7 ]
TSSFS [1 ]
TSSFS [2 ]
TSSFS [6 ]
TSSFS [8 ]
RD_R/W
(continued)
d
indicates an internal pull-down.
O
O
O
I
I
u
Receive Framer CRC-4 Multiframe Sync. This active-high signal is
the CEPT CRC-4 multiframe synchronization pulse in the receive
framer.
Transmit Framer Signaling Superframe Sync. This signal is the
CEPT signaling superframe (multiframe) synchronization pulse in the
transmit framer. This signal is active-high.
Transmit Framer CRC-4 Multiframe Sync. This signal is the CEPT
CRC-4 submultiframe synchronization pulse in the transmit framer. This
signal is active-high.
MPMODE. Strap to ground to enable the Motorola 68360 microproces-
sor protocol (MODE1). Strap to V
processor protocol (MODE3).
Read (Active-Low). In the Intel interface mode, the TFRA08C13 drives
the data bus with the contents of the addressed register while RD is
low. Read/Write. In the Motorola interface mode, this signal is asserted
high for read accesses; this pin is asserted low for write accesses.
TFRA08C13 OCTAL T1/E1 Framer
DD
to enable the Intel 80X86/88 micro-
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