tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 3

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Contents
Phase-Lock Loop Circuit .........................................................................................................................................96
Framer-System Interface ........................................................................................................................................98
Concentration Highway Interface ............................................................................................................................98
JTAG Boundary-Scan Specification ..................................................................................................................... 105
Microprocessor Interface.......................................................................................................................................111
Reset.................................................................................................................................................................... 118
Interrupt Generation ..............................................................................................................................................118
Register Architecture.............................................................................................................................................119
Global Register Architecture .................................................................................................................................123
Global Register Structure......................................................................................................................................123
Framer Register Architecture ................................................................................................................................127
FDL Register Architecture.....................................................................................................................................168
FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);
(B20—B2E) (C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E)) .................................................................169
Receive Facility Data Link Interface.....................................................................................................................84
Transmit Facility Data Link Interface....................................................................................................................90
HDLC Operation ..................................................................................................................................................91
Transparent Mode................................................................................................................................................93
Diagnostic Modes ................................................................................................................................................95
DS1 Modes ..........................................................................................................................................................98
CEPT Modes........................................................................................................................................................98
Receive Elastic Store...........................................................................................................................................98
Transmit Elastic Store..........................................................................................................................................98
CHI Parameters ...................................................................................................................................................99
CHI Frame Timing..............................................................................................................................................101
CHI Offset Programming....................................................................................................................................104
Principle of the Boundary Scan..........................................................................................................................105
Test Access Port Controller ...............................................................................................................................107
Instruction Register ............................................................................................................................................109
Boundary-Scan Register....................................................................................................................................110
BYPASS Register ..............................................................................................................................................110
DCODE Register................................................................................................................................................110
3-State Procedures ............................................................................................................................................110
Overview ............................................................................................................................................................111
Microprocessor Configuration Modes ................................................................................................................111
Microprocessor Interface Pinout Definitions ......................................................................................................112
Microprocessor Clock (MPCLK) Specifications .................................................................................................112
Microprocessor Interface Register Address Map ...............................................................................................113
I/O Timing ..........................................................................................................................................................113
Hardware Reset (Pin C19).................................................................................................................................118
Software Reset/Software Restart.......................................................................................................................118
Framer Block Interrupt Status Register (GREG0)..............................................................................................123
Framer Block Interrupt Enable Register (GREG1).............................................................................................124
FDL Block Interrupt Status Enable Register (GREG2) ......................................................................................124
FDL Block Interrupt Enable Register (GREG3) .................................................................................................124
Global Control Register (GREG4)......................................................................................................................125
Device ID and Version Registers (GREG5—GREG7) .......................................................................................125
Global Control Register (GREG8)......................................................................................................................126
Global PLLCK Control Register (GREG9) .........................................................................................................127
Framer Status/Counter Registers ......................................................................................................................128
Framer Parameter/Control Registers .................................................................................................................141
Table of Contents
(continued)
TFRA08C13 OCTAL T1/E1 Framer
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