tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 94

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link
In the transmit direction, the FDL HDLC takes data
from the transmit FIFO and transmits that data exactly
bit-for-bit on the TFDL interface. Transmit data is octet-
aligned to the first TFDLCK after the transmitter has
been enabled. The bits are transmitted least significant
bit first. When there is no data in the transmit FIFO, the
FDL HDLC either transmits all ones, or transmits the
programmed HDLC transmitter idle character (register
FDL_PR5) if register FDL_PR9 bit 6 (FMATCH) is set
to 1. To cause the transmit idle character to be sent
first, the character must be programmed before the
transmitter is enabled.
The transmitter empty interrupt, register FDL_SR0 bit 1
(FTEM), acts as in the HDLC mode. The transmitter-
done interrupt, register FDL_SR0 bit 0 (FTDONE), is
used to report an empty FDL transmit FIFO. The
FTDONE interrupt thus provides a way to determine
transmission end. Register FDL_SR0 bit 2 (FTUND-
ABT) interrupt is not active in the transparent mode.
In the receive direction, the FDL HDLC block loads
received data from the RFDL interface directly into the
receive FIFO bit-for-bit. The data is assumed to be
least significant bit first. If FMATCH register FDL_PR9
bit 6 is 0, the receiver begins loading data into the
receive FIFO beginning with the first RFDLCK detected
after the receiver has been enabled. If the FMATCH bit
is set to 1, the receiver does not begin loading data into
the FIFO until the receiver match character has been
detected. The search for the receiver match character
is in a sliding window fashion if register FDL_PR9 bit 4
Table 44. Receiver Operation in Transparent Mode
Note: The match bit (FMATCH) affects both the transmitter and the receiver. Care should be taken to correctly program both the transmit idle
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FALOCT
character and the receive match character before setting FMATCH. If the transmit idle character is programmed to FF (hex), the FMATCH
bit appears to affect only the receiver.
X
0
1
FMATCH
0
1
1
(continued)
Serial-to-parallel conversion begins with first RFDLCK after FRE, register
FDL_PR1 bit 2, is set. Data loaded to receive FIFO immediately.
Match user-defined character using sliding window. Byte aligns once character is
recognized. No data to receive FIFO until match is detected.
Match user-defined character, but only on octet boundary. Boundary based on
first RFDLCK after FRE, register FDL_PR1 bit 2, set. No data to receive FIFO
until match is detected.
(FALOCT) bit is 0 (align to octet), or only on octet
boundaries if FALOCT is set to 1. The octet boundary
is aligned relative to the first RFDLCK after the receiver
has been enabled. The matched character and all sub-
sequent bytes are placed in the receive FIFO. An FDL
receiver reset, register FDL_PR1 bit 4 (FRR) = 1,
causes the receiver to realign to the match character if
FMATCH is set to 1.
The receiver full (FRF) and receiver overrun
(FROVERUN) interrupts in register FDL_SR0 act as in
the HDLC mode. The received end of frame (FREOF)
and receiver idle (FRIDL) interrupts are not used in the
transparent mode. The match status (FMSTAT) bit is
set to 1 when the receiver match character is first rec-
ognized. If the FMATCH bit is 0, the FMSTAT
(FDL_PR9 bit 3) bit is set to 1 automatically when the
first bit is received, and the octet offset status bits
(FDL_PR9 bit 0—bit 2) read 000. If the FMATCH bit is
programmed to 1, the FMSTAT bit is set to 1 upon rec-
ognition of the first receiver match character, and the
octet offset status bits indicate the offset relative to the
octet boundary at which the receiver match character
was recognized. The octet offset status bits have no
meaning until the FMSTAT bit is set to 1. An octet offset
of 111 indicates byte alignment.
An interrupt for recognition of the match character can
be generated by setting the FRIL level to 1. Since the
matched character is the first byte written to the FIFO,
the FRF interrupt occurs with the writing of the match
character to the receive FIFO.
The operation of the receiver in transparent mode is
summarized in Table 44.
Receiver Operation
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000