tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 19

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Pin Information
Table 2. Pin Descriptions (continued)
Lucent Technologies Inc.
Lucent Technologies Inc.
† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
‡ Asserting this pin low will initially force RDY to a low state.
* I
u
H26, J24
indicates an internal pull-up, I
AD19
AC20
Pins
AE9
D18
A19
H24
G25
G26
H23
AE5
B12
T25
F26
V1
J4
DS1/CEPT[1 ]
DS1/CEPT[2 ]
DS1/CEPT[3 ]
DS1/CEPT[4 ]
DS1/CEPT[5 ]
DS1/CEPT[6 ]
DS1/CEPT[7 ]
DS1/CEPT[8 ]
CHICK-EPLL
PLLCK-EPLL
DIV-PLLCK
DIV-CHICK
DIV-RLCK
SECOND
Symbol
CHICK
CHIFS
(continued)
d
indicates an internal pull-down.
Type*
O
O
O
O
O
O
I
I
I
u
Second Pulse. A one second timer with an active-high pulse. The
duration of the pulse is one RLCK cycle. Framer_1’s receive line clock
signal (RLCK1) is the default clock source for the internal second pulse
timer. The internal second pulse is retimed in the individual framer sec-
tions with their corresponding receive line clock signal RLCK. When
LORLCK_(N) is active, then Framer_(N + 1)’s receive line clock signal
is used as the clock signal source for the internal second pulse timer.
The second pulse is used for performance monitoring.
CHI Clock. 2.048 MHz,
4.096 MHz, or 8.192 MHz.
CHI Frame Sync. CHI 8 kHz input frame synchronization pulse. Pulse
width must be a minimum of one clock period of CHICK and a maxi-
mum of a 50% duty cycle square wave.
Error Phase-Lock Loop Signal. The error signal proportional to the
phase difference between DIV-CHICK and DIV-RLCK as detected from
the internal PLL circuitry (see Table 66. Global Control Register
(GREG8) (008)
Divided-Down PLLCK Clock. 32 kHz or 8 kHz clock signal derived
from the PLLCK input signal (see Table 150. CHI Common Control
Register (FRM_PR45) (Y8D)).
Error Phase-Lock Loop Signal. The error signal proportional to the
phase difference between DIV-PLLCK and DIV-CHICK as detected by
the internal PLL circuitry (refer to the Phase-Lock Loop section).
Divided-Down Receive Line Clock. 8 kHz clock signal derived from
the recovered receive line interface unit clock or the RLCK input signal.
The choice of which receive framer clock to use is defined in Table 66.
Global Control Register (GREG8) (008).
Divided-Down CHI Clock. 8 kHz clock signal derived from the transmit
CHI CLOCK input signal (see Table 66. Global Control Register
(GREG8) (008)).
DS1/CEPT. Strap to V
Strap to V
SS
to enable CEPT operation in the framer unit.
DD
to enable DS1 operation in the framer unit.
TFRA08C13 OCTAL T1/E1 Framer
Description
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