tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 161

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Framer Register Architecture
CHI Common Control Register (FRM_PR45)
These bits define the common attributes of the CHI for TCHIDATA, TCHIDATAB, RCHIDATA, and RCHDATAB. The
default value of this register is 00 (hex).
Table 150. CHI Common Control Register (FRM_PR45) (Y8D)
2—3
5—6
Bit
0
1
4
7
CDRS0—
HWYEN
Symbol
CDRS1
CHIMM
HFLF
CMS
—
High-Frequency/Low-Frequency PLLCK Clock Mode. A 0 enables the low-frequency
PLLCK mode for the divide-down circuit in the internal phase-lock loop section (DS1
PLLCK = 1.544 MHz; CEPT PLLCK = 2.048 MHz). The divide-down circuit will produce
an 8 kHz signal on DIV-PLLCK, pin G25. A 1 enables the high-frequency PLLCK mode
for the divide-down circuit in the internal phase-lock loop section (DS1: PLLCK = 6.176
(4 x 1.544) MHz; CEPT: 8.192 (4 x 2.048) MHz). The divide-down circuit will produce a
32 kHz signal on DIV-PLLCK.
Concentration Highway Clock Mode. A 0 enables the CHI clock frequency and CHI
data rate to be equal. Function of CMS = 1 is reserved. This control bit affects both the
transmit and receive interfaces.
Concentration Highway Interface Data Rate Select.
Concentration Highway Master Mode. A 0 enables external system’s frame synchroni-
zation signal (CHIFS) to drive the transmit path of the framer’s concentration highway
interface. A 1 enables the framer’s transmit concentration interface to generate a system
frame synchronization signal derived from the receive line interface. The framer’s system
frame synchronization signal is generated on the CHIFS output pin. Applications using
the receive line clock as the reference clock signal of the system are recommended to
enable this mode and use the CHIFS signal generated by the framer. The receive CHI
path is not affected by this mode.
Reserved. Write to 0.
Highway Enable. A 1 in this bit position enables transmission to the concentration high-
way. This allows the TFRA08C13 to be fully configured before transmission to the high-
way. A 0 forces the idle code as defined in register FRM_PR22 to be transmitted to the
line in all payload time slots and the transmit CHI pin is forced to a high-impedance state
for all CHI transmitted time slots.
(continued)
Bits
2 3
0 0
0 1
1 0
1 1
Description
CHI Data Rate
2.048 Mbits/s
4.096 Mbits/s
8.192 Mbits/s
Reserved
TFRA08C13 OCTAL T1/E1 Framer
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