tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 152

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture
Framer Reset and Transparent Mode Control Register (FRM_PR26)
The default value of this register is 00 (hex).
Table 136. Framer Reset and Transparent Mode Control Register (FRM_PR26) (Y7A)
152
6—7
Bits
0
1
2
3
4
5
SWRESTART Framer Software Restart. The framer and FDL sections are placed in the reset state as
SWRESET
SYSFSM
Symbol
FRFRM
TFM1
TFM2
—
Framer Software Reset. The framer and FDL sections are placed in the reset state for
four clock cycles of the frame internal line clock (RFRMCK). The parameter registers are
forced to the default values. This bit is self-cleared.
long as this bit is set to 1. The framer’s parameter registers are not changed from their
programmed state. The FDL parameter registers are changed from their programmable
state. This bit must be cleared.
Framer Reframe. A 0-to-1 transition of this bit forces the receive framer into the loss of
frame alignment (LFA) state which forces a search of frame alignment. Subsequent
reframe commands must have this bit in the 0 state first.
Transparent Framing Mode 1. A 1 forces the transmit framer to pass system data
unmodified to the line and the receive framer to pass line data unmodified to the system.
The receive framer is forced not to align to the input receive data.
DS1: register FRM_PR43 bit 2—bit 0 must be set to 000. The F bit is located in time slot
0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and places this
bit in the F-bit position of the transmit line data. The receive framer inserts the bit in the
F-bit position of the receive line data into time slot 0, bit 7 of the TCHIDATA.
CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data. Receive
line time slot 0 is inserted into time slot 0 of TCHIDATA.
Transparent Framing Mode 2. A 1 forces the transmit framer to pass system data
unmodified to the line. The receive framer functions normally as programmed.
DS1: register FRM_PR43 bit 2—bit 0 must be set to 000. The F bit is located in
time slot 0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and
places this bit in the F-bit position of the transmit line data.
CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data.
System Frame Sync Mask. A 1 masks the system frame synchronization signal in the
transmit framer section.
Note: The transmit framer must see at least one valid system synchronization pulse to
Reserved. Write to 0.
initialize its counts; afterwards, this bit may be set. For those applications that
have jitter on the transmit clock signal relative to the system clock signal, enable
this bit so that the jitter is isolated from the transmit framer.
(continued)
Description
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000