tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 170

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);
(B20—B2E) (C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E))
Table 167. FDL Interrupt Mask Control Register (FDL_PR2) (A02; A22; B02; B22; C02; C22; D02; D22)
170
Bit
0
1
2
3
4
5
6
7
FREOFIE
FTUNDIE
FTBCRC
FROVIE
Symbol
FTDIE
FRFIE
FTEIE
FRIIE
FDL Transmit-Done Interrupt Enable. When this interrupt enable bit is set, an
INTERRUPT pin transition is generated after the last bit of the closing flag or abort
sequence is sent. In the transparent mode (register FDL_PR9 bit 6 = 1), an INTERRUPT
pin transition is generated when the transmit FIFO is completely empty. FTDIE is cleared
upon reset.
FDL Transmitter-Empty Interrupt Enable. When this interrupt-enable bit is set, an
INTERRUPT pin transition is generated when the transmit FIFO has reached the pro-
grammed empty level (see register FDL_PR3). FTEIE is cleared upon reset.
FDL Transmit Underrun Interrupt Enable. When this interrupt-enable bit is set, an
INTERRUPT pin transition is generated when the transmit FIFO has underrun. FTUNDIE
is cleared upon reset and is not used in the transparent mode.
FDL Receiver-Full Interrupt Enable. When this interrupt-enable bit is set, an
INTERRUPT pin transition is generated when the receive FIFO has reached the pro-
grammed full level (see register FDL_PR6). FRFIE is cleared upon reset.
FDL Receive End-of-Frame Interrupt Enable. When this interrupt-enable bit is set, an
INTERRUPT pin transition is generated when an end-of-frame is detected by the FDL
receiver. FREOFIE is cleared upon reset and is not used in the transparent mode.
FDL Receiver Overrun Interrupt Enable. When this interrupt-enable bit is set, an
INTERRUPT pin transition is generated when the receive FIFO overruns. FROVIE is
cleared upon reset.
FDL Receiver Idle-Interrupt Enable. When this interrupt-enable bit is set, an
INTERRUPT pin transition is generated when the receiver enters the idle state. FRIIR is
cleared upon reset and is not used in the transparent mode.
FDL Transmit Bad CRC. Setting this bit to 1 forces bad CRCs to be sent on all transmit-
ted frames (for test purposes) until the FTBCRC bit is cleared to 0.
Description
Preliminary Data Sheet
(continued)
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000