tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 128

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture
Framer Status/Counter Registers
Registers FRM_SR0—FRM_SR63 report the status of each framer. All are clear-on-read, read-only registers.
Interrupt Status Register (FRM_SR0)
The interrupt pin (INTERRUPT) goes active when a bit in this register and its associated interrupt enable bit in reg-
isters FRM_PR0—FRM_PR7 are set, and the interrupt for the framer block is enabled in register GREG1.
Table 69. Interrupt Status Register (FRM_SR0) (Y00)
128
Bit
0
1
2
3
4
5
6
7
Symbol
RSSFE
TSSFE
S96SR
RAC
ESE
FAC
FAE
—
Facility Alarm Condition. A 1 indicates a facility alarm occurred (go read FRM_SR1).
Remote Alarm Condition. A 1 indicates a remote alarm occurred (go read FRM_SR2).
Facility Alarm Event. A 1 indicates a facility alarm occurred (go read FRM_SR3 and
FRM_SR4).
Errored Second Event. A 1 indicates an errored second event occurred (go read
FRM_SR5, FRM_SR6, and FRM_SR7).
Transmit Signaling Superframe Event. A 1 indicates that a MOS superframe block
has been transmitted and the transmit signaling data buffers are ready for new data.
Receive Signaling Superframe Event. A 1 indicates that a MOS superframe block has
been received and the receive signaling data buffers must be read.
Reserved.
SLC -96 Stack Ready. A 1 indicates that either the transmit framer SLC -96 stack is
ready for more data or the receive framer SLC -96 stack contains new data.
(continued)
Description
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000