tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 142

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture
Primary Interrupt Enable Register (FRM_PR0)
The default value of this register is 00 (hex).
Table 107. Primary Interrupt Group Enable Register (FRM_PR0) (Y60)
Secondary Interrupt Enable Registers (FRM_PR1—FRM_PR7)
A bit set to 1 in registers FRM_PR1—FRM_PR7 enables the generation of interrupts whenever the corresponding
bit in registers FRM_SR1—FRM_SR7 is set. The default value of these registers is 00 (hex).
Table 108. Interrupt Enable Register (FRM_PR1) (Y61)
Table 109. Interrupt Enable Register (FRM_PR2) (Y62)
Table 110. Interrupt Enable Register (FRM_PR3) (Y63)
142
0—7
0—7
0—7
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
SR1B0IE—
SR2B0IE—
SR3B0IE—
SR1B7IE
SR2B7IE
SR3B7IE
SR567IE
Symbol
Symbol
Symbol
Symbol
SR34IE
RSRIE
TSRIE
SR1IE
SR2IE
SLCIE
—
Status Register 1 Interrupt Enable Bit. A 1 enables register FRM_SR1 event inter-
rupts.
Status Register 2 Interrupt Enable Bit. A 1 enables register FRM_SR2 event inter-
rupts.
Status Registers 3 and 4 Interrupt Enable Bit. A 1 enables registers FRM_SR3 and
FRM_SR4 event interrupts.
Status Registers 5, 6, and 7 Interrupt Enable Bit. A 1 enables registers FRM_SR5,
FRM_SR6, and FRM_SR7 event interrupts.
Transmit Signaling Ready Interrupt Enable Bit. A 1 enables interrupts when transmit
signaling buffers are ready (MOS mode).
Receive Signaling Ready Interrupt Enable Bit. A 1 enables interrupts when receive
signaling buffers are ready (MOS mode).
Reserved. Write to 0.
SLC -96 Interrupt Enable Bit. A 1 enables interrupts when SLC -96 receive or transmit
stacks are ready.
Status Register 1 Interrupt Enable. A 1 enables events monitored in register
FRM_SR1 to generate interrupts. Each bit position in this enable register corresponds to
the same bit position in the status register.
Status Register 2 Interrupt Enable. A 1 enables events monitored in register
FRM_SR2 to generate interrupts. Each bit position in this enable register corresponds to
the same bit position in the status register.
Status Register 3 Interrupt Enable. A 1 enables events monitored in register
FRM_SR3 to generate interrupts. Each bit position in this enable register corresponds to
the same bit position in the status register.
(continued)
Description
Description
Description
Description
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000