tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 20

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Pin Information
Table 2. Pin Descriptions (continued)
20
† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
‡ Asserting this pin low will initially force RDY to a low state.
* I
u
indicates an internal pull-up, I
AC10
AE26
AC19
AE22
AE20
AF19
AF22
Pins
W26
AD4
AE3
R26
C12
AE4
R25
K23
A20
F25
E23
T26
E25
A12
E26
B11
D5
V3
D7
R4
G1
U1
G2
U2
L1
F1
LOPLLCK
PLLCK [1 ]
PLLCK [2 ]
PLLCK [3 ]
PLLCK [4 ]
PLLCK [5 ]
PLLCK [6 ]
PLLCK [7 ]
PLLCK [8 ]
TLCK [1 ]
TLCK [2 ]
TLCK [3 ]
TLCK [4 ]
TLCK [5 ]
TLCK [6 ]
TLCK [7 ]
TLCK [8 ]
Symbol
TND [3 ]
TND [4 ]
TPD [1 ]
TPD [2 ]
TPD [3 ]
TPD [4 ]
TPD [5 ]
TPD [6 ]
TPD [7 ]
TPD [8 ]
TND [1 ]
TND [2 ]
TND [5 ]
TND [6 ]
TND [7 ]
TND [8 ]
(continued)
d
indicates an internal pull-down.
Type*
O
O
O
O
I
Transmit Framer Phase-Locked Line Interface Clock. Clock signal
used to time the transmit framer. This signal must be phase-locked to
CHICK clock signal. In DS1 frame formats, PLLCK can be a low-
frequency signal (1.544 MHz) or a high frequency signal (6.176 MHz).
In CEPT frame formats, PLLCK can be a low-frequency signal
(2.048 MHz) or a high-frequency signal (8.192 MHz).
Loss of PLLCK Clock. This pin is asserted high when the PLLCK
clock does not toggle for a 250 µs interval. This pin is deasserted
250 s after the first edge of PLLCK (see Table 66. Global Control Reg-
ister (GREG8) (008)).
Transmit Framer Line Interface Clock. Optional 1.544 MHz DS1 or
2.048 MHz output signal from the transmit framer . TND and TPD data
changes on the rising edge of TLCK.
Transmit Line Interface Positive-Rail Data. This signal is the transmit
framer positive NRZ output data. Data changes on the rising edge of
TLCK. In the single-rail mode, TPD = transmit framer data.
Transmit Line Interface Negative-Rail Data. This signal is the trans-
mit framer negative NRZ output data. Data changes on the rising edge
of TLCK. In the single-rail mode, TND = 0.
Description
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000