tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 61

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
CEPT Time Slot 0 FAS/NOT FAS Control
Bits
Interrupts indicating that the transmit Sa stack or the
receive Sa stack are ready for system access are avail-
able, see register FRM_SR4 bit 6 and bit 7.
CEPT Time Slot 16 X0—X2 Control Bits
Each of the three X bits in frame 0 of the time slot 16
multiframe can be used as a 0.5 kbits/s data link to and
from the remote end. The transmitted line X bits are
sourced from control register FRM_PR41 bit 0—bit 2.
In the loss of TS16 multiframe alignment (LTS16MFA)
state, receive X bits are set to 1 in status register
FRM_SR53.
Signaling Access
Signaling information can be accessed by three differ-
ent methods: transparently through the CHI, via the
control registers, or via the CHI associated signaling
mode.
Transparent Signaling
This mode is enabled by setting register FRM_PR44 bit
0 to 1.
Data at the received RCHIDATA interface passes
through the framer undisturbed. The framer generates
an arbitrary signaling multiframe in the transmit and
receive directions to facilitate the access of signaling
information at the system interface.
DS1: Robbed-Bit Signaling
Microprocessor Control Registers
To enable signaling, register FRM_PR44 bit 0 must be
set to 0 (default).
The information written into the F and G bits of the
transmit signaling registers, FRM_TSR0—
FRM_TSR23, define the robbed-bit signaling mode for
each channel for both the transmit and receive direc-
tions. The per-channel programming allows the system
to combine voice channels with data channels within
the same frame.
(continued)
The receive-channel robbed-bit signaling mode is
always defined by the state of the F and G bits in the
corresponding transmit signaling registers for that
channel. The received signaling data is stored in the
receive signaling registers, FRM_RSR0—
FRM_RSR23, while receive framer is in both the frame
and superframe alignment states. Updating the receive
signaling registers can be inhibited on-demand, by set-
ting register FRM_PR44 bit 3 to 1, or automatically
when either a framing error event, a loss of frame, or
superframe alignment state is detected or a controlled
slip event occurs. The signaling inhibit state is valid for
at least 32 frames after any one of the following: a
framing errored event, a loss of frame and/or super-
frame alignment state, or a controlled slip event.
In the common channel signaling mode, data written in
the transmit signaling registers is transmitted in chan-
nel 24 of the transmit line bit stream. The F and G bits
are ignored in this mode. The received signaling data
from channel 24 is stored in receive signaling registers
FRM_RSR0—FRM_RSR23 for T1.
Associated Signaling Mode
This mode is enabled by setting register FRM_PR44 bit
2 to 1.
Signaling information in the associated signaling mode
(ASM) is allocated an 8-bit system time slot in conjunc-
tion with the payload data information for a particular
channel. The default system data rate in the ASM
mode is 4.096 Mbits/s. Each system channel consists
of an 8-bit payload time slot followed by its correspond-
ing 8-bit signaling time slot. The format of the signaling
byte is identical to that of the signaling registers.
In the ASM mode, writing the transmit signaling regis-
ters will corrupt the transmit signaling data. In the trans-
mit signaling register ASM (TSR-ASM) format, enabled
by setting register FRM_PR44 bit 2 and bit 5 to 1, the
system must write into the F and G bit
signaling registers to program the robbed-bit signaling
state mode of each DS0. The ABCD bits are sourced
from the RCHI ports when TSR-ASM mode is enabled.
* All other bits in the signaling registers are ignored, while the F and
G bits in the received RCHIDATA stream are ignored.
TFRA08C13 OCTAL T1/E1 Framer
*
of the transmit
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