tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 21

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Pin Information
Table 2. Pin Descriptions (continued)
Lucent Technologies Inc.
Lucent Technologies Inc.
† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
‡ Asserting this pin low will initially force RDY to a low state.
* I
u
indicates an internal pull-up, I
AD10
AE13
AA24
AE12
AF11
Pins
W25
M25
M24
C22
AA2
Y26
D20
Y24
C21
A21
L25
L26
W3
M4
D2
P2
Y3
B8
B1
B7
B3
N2
D8
C5
Y1
A7
L3
RCHIDATA[1 ]
RCHIDATA[2 ]
RCHIDATA[3 ]
RCHIDATA[4 ]
RCHIDATA[5 ]
RCHIDATA[6 ]
RCHIDATA[7 ]
RCHIDATA[8 ]
TFDLCK[1 ]
TFDLCK[2 ]
TFDLCK[3 ]
TFDLCK[4 ]
TFDLCK[5 ]
TFDLCK[6 ]
TFDLCK[7 ]
TFDLCK[8 ]
Symbol
TFDL[1 ]
TFDL[2 ]
TFDL[3 ]
TFDL[4 ]
TFDL[5 ]
TFDL[6 ]
TFDL[7 ]
TFDL[8 ]
TFS[1 ]
TFS[2 ]
TFS[3 ]
TFS[4 ]
TFS[5 ]
TFS[6 ]
TFS[7 ]
TFS[8 ]
(continued)
d
indicates an internal pull-down.
Type*
O
O
I
I
Transmit Framer Frame Sync. This signal is the 8 kHz frame synchro-
nization pulse in the transmit framer. This signal is active-high.
Transmit Facility Data Link Clock. In DS1-DDS with data link access,
this is an 8 kHz clock signal; otherwise, 4 kHz. The transmit frame
latches data link bits on the falling edge of TFDLCK.
Transmit Facility Data Link. Optional serial input facility data link bit
stream inserted into the transmit line data stream by the transmit
framer. In DS1-DDS with data link access, this is an 8 kbits/s signal;
otherwise, 4 kbits/s. In the CEPT frame format, TFDL can be pro-
grammed to one of the XSa bits of the NOT FAS frame time slot 0.
Receive CHI Data. Serial input system data at 2.048 Mbits/s,
4.096 Mbits/s, or 8.192 Mbits/s.
TFRA08C13 OCTAL T1/E1 Framer
Description
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