tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 163

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Framer Register Architecture
CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52)
These four registers define which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHIDATAB
time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. The default value of this register is 00 (hex).
Table 154. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) (Y91—Y94)
CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56)
These four registers define which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCHIDATAB
time slots. A 0 disables the time slot and transmits the programmable idle code of register FRM_PR22 to the line in
the corresponding time slot. The default value of this register is FF (hex).
Table 155. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) (Y95—Y98)
CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60)
These four registers define which transmit CHI highway TCHIDATA or TCHIDATAB contains valid data for the active
time slot. A 0 enables TCHIDATA, and a 1 enables TCHIDATAB. The default value of this register is 00 (hex).
Table 156. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) (Y99—Y9C)
CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64)
These four registers define which receive CHI highway RCHIDATA or RCHIDATAB contains valid data for the active
time slot. A 0 enables RCHIDATA and a 1 enables RCHIDATAB. The default value of these registers is 00 (hex).
Table 157. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) (Y9D—YA0)
FRM_PR49
FRM_PR50
FRM_PR51
FRM_PR52
FRM_PR53
FRM_PR54
FRM_PR55
FRM_PR56
FRM_PR57
FRM_PR58
FRM_PR59
FRM_PR60
FRM_PR61
FRM_PR62
FRM_PR63
FRM_PR64
Register
Register
Register
Register
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
7—0
Bit
Bit
Bit
Bit
RTSE31—RTSE24 Receive Time-Slot Enable Bits 31—24.
RTSE23—RTSE16 Receive Time-Slot Enable Bits 23—16.
TTSE31—TTSE24 Transmit Time-Slot Enable Bits 31—24.
TTSE23—TTSE16 Transmit Time-Slot Enable Bits 23—16.
RTSE15—RTSE8 Receive Time-Slot Enable Bits 15—8.
TTSE15—TTSE8 Transmit Time-Slot Enable Bits 15—8.
RTSE7—RTSE0
RHS31—RHS24
RHS23—RHS16
THS31—THS24
THS23—THS16
TTSE7—TTSE0
RHS15—RHS8
THS15—THS8
RHS7—RHS0
THS7—THS0
Symbol
Symbol
Symbol
Symbol
(continued)
Transmit Time-Slot Enable Bits 7—0.
Receive Time-Slot Enable Bits 7—0.
Transmit Highway Select Bits 31—24.
Transmit Highway Select Bits 23—16.
Transmit Highway Select Bits 15—8.
Transmit Highway Select Bits 7—0.
Receive Highway Select Bits 31—24.
Receive Highway Select Bits 23—16.
Receive Highway Select Bits 15—8.
Receive Highway Select Bits 7—0.
TFRA08C13 OCTAL T1/E1 Framer
Description
Description
Description
Description
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