tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 49

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Frame Formats
CEPT Time Slot 0 CRC-4 Multiframe Structure
The CRC-4 multiframe is in bit 1 of each NOT FAS frame. As described in ITU Rec. G.704 Section 2.3.3.1, where
there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there
is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy
check-4 (CRC-4) procedure as detailed below. The allocation of bits 1—8 of time slot 0 of every frame is shown in
Table 20 for the complete CRC-4 multiframe.
Table 20. ITU CRC-4 Multiframe Structure
Notes:
C1 to C4 = cyclic redundancy check-4 (CRC-4) bits.
E = CRC-4 error indication bits.
Sa4 to Sa8 = spare bits.
A = remote frame alarm (RFA) bit (active-high); referred to as the A bit.
The CRC-4 multiframe consists of 16 frames numbered 0 to 15 and is divided into two eight-frame submultiframes
(SMF), designated SMF-I and SMF-II that signifies their respective order of occurrence within the CRC-4 multi-
frame structure. The SMF is the CRC-4 block size (2048 bits). In those frames containing the frame alignment sig-
nal (FAS), bit 1 is used to transmit the CRC-4 bits. There are four CRC-4 bits, designated C1, C2, C3, and C4 in
each SMF. In those frames not containing the frame alignment signal (NOT FAS), bit 1 is used to transmit the 6-bit
CRC-4 multiframe alignment signal and two CRC-4 error indication bits (E). The multiframe alignment signal is
defined in ITU Rec. G.704 Section 2.3.3.4, as 001011. Transmitted E bits should be set to 0 until both basic frame
and CRC-4 multiframe alignment are established. Thereafter, the E bits should be used to indicate received errored
submultiframes by setting the binary state of one E bit from 1 to 0 for each errored submultiframe. The received E
bits will always be taken into account, by the receive E-bit processor
found to be errored. In the case where there exists equipment that does not use the E bits, the state of the E bits
should be set to a binary 1 state.
* The receive E-bit processor will halt the monitoring of the received E bit during the loss of CRC-4 multiframe alignment.
Multiframe
Submultiframe
(continued)
(SMF)
II
I
Number
Frame
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
C1
C2
C3
C4
C1
C2
C3
C4
E
E
1
0
0
1
0
1
1
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
A
A
A
A
A
A
A
3
0
0
0
0
0
0
0
0
*
, even when the SMF that contains them is
TFRA08C13 OCTAL T1/E1 Framer
Sa4
Sa4
Sa4
Sa4
Sa4
Sa4
Sa4
Sa4
4
1
1
1
1
1
1
1
1
Bits
Sa5
Sa5
Sa5
Sa5
Sa5
Sa5
Sa5
Sa5
5
1
1
1
1
1
1
1
1
Sa6
Sa6
Sa6
Sa6
Sa6
Sa6
Sa6
Sa6
6
0
0
0
0
0
0
0
0
Sa7
Sa7
Sa7
Sa7
Sa7
Sa7
Sa7
Sa7
7
1
1
1
1
1
1
1
1
Sa8
Sa8
Sa8
Sa8
Sa8
Sa8
Sa8
Sa8
8
1
1
1
1
1
1
1
1
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