tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 149

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Framer Register Architecture
Framer FDL Control Command Register (FRM_PR21)
The default value of this register is 00 (hex).
Table 129. Framer FDL Control Command Register (FRM_PR21) (Y75)
Framer Transmit Line Idle Code Register (FRM_PR22)
The value programmed in this register is transmitted as the line idle code. The default value is 7F (hex).
Table 130. Framer Transmit Line Idle Code Register (FRM_PR22) (Y76)
Framer System Stuffed Time-Slot Code Register (FRM_PR23)
The value programmed in this register is transmitted in the stuffed time slots on the CHI in the DS1 modes. The
default value is 7F (hex).
Table 131. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (Y77)
0—7
0—7
Bit
Bit
Bit
0
1
2
3
4
5
6
7
TFDLSAIS
TFDLLAIS
TLIC0—TLIC7
Symbol
TC/R=1
TFDLC
SSTSC0—
SSTSC7
Symbol
Symbol
—
—
—
—
Reserved. Must be set to 0.
Reserved. Must be set to 0.
Reserved. Must be set to 0.
Reserved. Must be set to 0.
Transmit Facility Data Link AIS to the Line. A 1 sends AIS in the line side data link.
Transmit Facility Data Link AIS to the System. A 1 sends AIS in the system data link
side.
Transmit FDL Control Bit. A 0 enables the transmission of the FDL bit from the internal
FDL-HDLC unit (default). A 1 enables the transmission of the FDL bit from the TFDL
input or from the internal transmit stack depending on the state of FRM_PR29
bit 5—bit 7. When the SLC -96 stack transmission is enabled (register FRM_PR26
bit 5—bit 7 = x10 (binary), the FDL bit is sourced from the SLC -96 transmit stack (regis-
ter FRM_PR31—FRM_PR35). Otherwise, it is sourced from TFDL.
Transmit ESF_PRM C/R = 1 (TC/R = 1). A 0 transmits the ESF performance report mes-
sage with the C/R bit = 0. (See ANSI T1.403-1995 for the PRM structure and content.) A
1 transmits the ESF performance report message with the C/R bit = 1.
T ransmit Line Idle Code 0—7. These 8 bits define the idle code transmitted to the
line.
System Stuffed Time-Slot Code 0—7. These 8 bits define the idle code transmitted
in the stuffed time slots to the system CHI.
(continued)
Description
Description
Description
TFRA08C13 OCTAL T1/E1 Framer
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