tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 186

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Electrical Characteristics
Logic Interface Characteristics
Table 188. Logic Interface Characteristics (T
* Sinking.
† Sourcing.
Notes:
All buffers use CMOS levels.
All inputs are driven between 2.4 V and 0.4 V.
An internal pull-up is provided on the 3-STATE, RESET, DS1/CEPT, MPMODE, CS, MPCK, TDI, TCK, and TMS pins.
An internal pull-down is provided on the TRST pin.
Power Supply Bypassing
External bypassing is required for each power supply pin. A 0.1 µF capacitor must be connected between each
V
separated, joining at a single point near the external ground connection. The need to reduce high-frequency cou-
pling into the analog supply (V
between these lines and the 3.3 V power plane.
Capacitors used for power supply bypassing should be placed as close as possible to the device pins.
186
Input Leakage Current
Output Voltage:
Input Capacitance
Load Capacitance:
DD
All Inputs Except Pulled-
Pulled-Up Pins
Pulled-Down Pins
Low
High
All Outputs Except D[7:0]
D[7:0]
Up and Pulled-Down Pins
and V
Parameter
SS
, between V
DDD
and V
DDA
) and quiet digital supply (V
Symbol
SSD
I
I
V
V
LPU
LPD
C
C
C
I
OH
OL
L
, and between V
L
L
I
A
= –40 °C to +85 °C, V
Test Conditions
I
OL
I
OH
DDA
= – 5.0 mA*
= 5.0 mA
—
—
—
—
—
—
and V
DDD
) may require inductive beads to be inserted
†
SSA
. The V
DD
= 3.3 V ± 5%, V
V
SS
DD
Min
, V
—
—
—
—
—
—
0
– 1.0
SSD
Preliminary Data Sheet
, and V
Lucent Technologies Inc.
SS
Lucent Technologies Inc.
SSA
= 0)
Max
V
±10
185
100
0.5
3.0
80
50
DD
planes should be
October 2000
Unit
µ A
µ A
µ A
pF
pF
pF
V
V