tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 145

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Framer Register Architecture
Alarm Filter Register (FRM_PR10)
The bits in this register enable various control options. The default setting is 00 (hex).
Table 118. Alarm Filter Register (FRM_PR10) (Y6A)
Bit 6 and bit 7 of FRM_PR10 control the evaluation of the bursty errored parameter as defined in Table 119 below.
The EST parameter refers to the errored second threshold defined in register FRM_PR11. The SEST parameter
refers to the severely errored second threshold defined in registers FRM_PR12 and FRM_PR13
Table 119. Errored Event Threshold Definition
FRM_PR10
Bit
0
1
2
3
4
5
ESM1
Bit 7,
Other Combinations
0
0
CNUCLBEN CNUCLB Enable (CEPT Only). A 0 enables payload loopback with regenerated framing
Symbol
SSa6M
FEREN
NFFE
RABF
AISM
—
FRM_PR10
ESM0
Bit 6,
0
1
Synchronous Sa6 Monitoring. A 0 enables the asynchronous monitoring of the Sa6
codes relative to the receive CRC-4 submultiframe. A 1 enables synchronous monitoring
of the Sa6 pattern relative to the receive CRC-4 submultiframe.
AIS Detection Mode. A 0 enables the detection of received line AIS as described in
ETSI Draft prETS 300 233:1992. A 1 enables the detection of received line AIS as
described in ITU Rec. G.775.
FER Enable (DS1 Only). A 0 enables only the detection of F
and SLC -96 modes. A 1 enables the detection of F
Not FAS Framing Bit Error Control (CEPT Only). A 0 enables the monitoring of
errored FAS and errored NOT FAS frames in the framing bit error counter, registers
FRM_SR10 and FRM_SR11. A 1 enables the monitoring of only errored FAS frames in
this error counter.
and CRC bits in register FRM_PR24. A 1 enables CEPT nailed-up connect loopback in
register FRM_PR24.
Reserved. Set to 0.
Receive A-Bit Filter (CEPT Only). A 0 makes the occurrence of three consecutive
A bit = 1 events assert and three consecutive A bit = 0 events deassert the remote frame
alarm, register FRM_SR2 bit 0. A 1 enables the occurrence of a single A-bit event to
deassert the remote frame alarm.
Reserved.
Default values in Table 32.
ES = 1 when:
Errored events > EST
Errored Second (ES)
Definition
(continued)
BES = 0
Bursty Errored Second
Description
(BES) Definition
TFRA08C13 OCTAL T1/E1 Framer
T
and F
S
framing bit errors.
T
SES = 1 when:
Errored events > SEST
framing bit errors in D4
Severely Errored
Second (SES)
Definition
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