DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 122

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Host Interface (HI08)
6.7.1 Interface Control Register (ICR)
The ICR is an 8-bit read/write control register by which the host processor controls the HI08
interrupts and flags. The DSP core cannot access the ICR. The ICR is a read/write register, which
allows the use of bit manipulation instructions on control register bits. Hardware and software
reset clear the ICR bits.
6-22
Bit Number
Host Address
7
0
1
2
3
4
5
6
7
Bit Name
INIT
Table 6-15. Interface Control Register (ICR) Bit Definitions
Big Endian HLEND = 0
INIT
Figure 6-15. Interface Control Register (ICR)
7
Reset Value
RXM/TXM
00000000
RXH/TXH
RXL/TXL
CVR
ICR
ISR
IVR
Table 6-14. Host-Side Register Map
0
6
DSP56303 User’s Manual, Rev. 2
HLEND
Initialize
The host processor uses INIT to force initialization of the HI08 hardware.
During initialization, the HI08 transmit and receive control bits are configured.
Use of the INIT bit to initialize the HI08 hardware depends on the software
design of the interface. The type of initialization when the INIT bit is set
depends on the state of TREQ and RREQ The INIT command, which is local
to the HI08, configures the HI08 into the desired data transfer mode. When
the host sets the INIT bit, the HI08 hardware executes the INIT command.
The interface hardware clears the INIT bit after the command executes.
5
—Reserved bit; read as 0; write to 0 for future compatibility.
TREQ
0
0
1
1
HF1
Little Endian HLEND = 1
4
HF0
RXM/TXM
00000000
RXH/TXH
RXL/TXL
RREQ
3
CVR
ICR
ISR
IVR
0
1
0
1
HDRQ TREQ RREQ
2
RXDF = 0; HTDE = 1;
After INIT Execution
RXDF = 0; HTDE = 1
TXDE = 1; HRDF = 0
TXDE = 1; HRDF = 0
Description
1
INIT = 0;
INIT = 0;
INIT = 0;
INIT = 0
0
Command Vector
Receive/Transmit
Interface Control
Register Name
Interface Status
Interrupt Vector
Freescale Semiconductor
Unused
Data
Transfer Direction
Host to/from DSP
Host to DSP
DSP to host
None