DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 87

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
Note:
Number
21–19
Bit
When DTM = 001 or 101, some peripherals can generate a second DMA request while the DMA controller is still
processing the first request (see the description of the DRS bits).
Bit Name
DTM
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Reset
Value
0
DMA Transfer Mode
Specify the operating modes of the DMA channel, as follows:
DTM[2–0
000
001
010
011
100
101
110
111
]
DSP56303 User’s Manual, Rev. 2
Trigger
request
request
request
request
request
DE
Cleared
After
Yes
Yes
Yes
Yes
DE
No
No
Block Transfer—DE enabled and DMA request
initiated. The transfer is complete when the counter
decrements to zero and the DMA controller reloads the
counter with the original value.
Word Transfer—A word-by-word block transfer (length
set by the counter) that is DE enabled. The transfer is
complete when the counter decrements to zero and the
DMA controller reloads the counter with the original
value.
Line Transfer—A line by line block transfer (length set
by the counter) that is DE enabled. The transfer is
complete when the counter decrements to zero and the
DMA controller reloads the counter with the original
value.
Block Transfer—The DE-initiated transfer is complete
when the counter decrements to zero and the DMA
controller reloads the counter with the original value.
Block Transfer—The transfer is enabled by DE and
initiated by the first DMA request. The transfer is
completed when the counter decrements to zero and
reloads itself with the original value. The DE bit is not
cleared at the end of the block, so the DMA channel
waits for a new request.
NOTE: The DMA End-of-Block-Transfer Interrupt
cannot be used in this mode.
Word Transfer—The transfer is enabled by DE and
initiated by every DMA request. When the counter
decrements to zero, it is reloaded with its original
value. The DE bit is not automatically cleared, so the
DMA channel waits for a new request.
NOTE: The DMA End-of-Block-Transfer Interrupt
cannot be used in this mode.
Description
Reserved
Reserved
DMA Control Registers 5–0 (DCR[5–0])
Transfer Mode
4-29