DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 69

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
Bit Number
5
4
3
2
1
0
Bit Name
E
U
N
V
C
Z
Table 4-2. Status Register Bit Definitions (Continued)
Reset Value
1
0
0
0
0
0
DSP56303 User’s Manual, Rev. 2
Extension
Cleared if all the bits of the integer portion of the 56-bit result are all ones or all
zeros; otherwise, this bit is set. The Scaling mode defines the integer portion.
If the E bit is cleared, then the low-order fraction portion contains all the
significant bits; the high-order integer portion is sign extension. In this case,
the accumulator extension register can be ignored. If the E bit is set, it
indicates that the accumulator extension register is in use.
Unnormalized
Set if the two MSBs of the Most Significant Portion (MSP) of the result are
identical; otherwise, this bit is cleared. The MSP portion of the A or B
accumulators is defined by the Scaling mode.
Negative
Set if the MSB of the result is set; otherwise, this bit is cleared.
Zero
Set if the result equals zero; otherwise, this bit is cleared.
Overflow
Set if an arithmetic overflow occurs in the 56-bit result; otherwise, this bit is
cleared. V indicates that the result cannot be represented in the accumulator
register (that is, the register overflowed). In Arithmetic Saturation mode, an
arithmetic overflow occurs if the Data ALU result is not representable in the
accumulator without the extension part (that is, 48-bit accumulator or the
32-bit accumulator in Arithmetic Sixteen-bit mode).
Carry
Set if a carry is generated by the MSB resulting from an addition operation.
This bit is also set if a borrow is generated in a subtraction operation;
otherwise, this bit is cleared. The carry or borrow is generated from Bit 55 of
the result. The C bit is also affected by bit manipulation, rotate, and shift
instructions.
S1
S1
0
0
1
1
0
0
1
1
S0
S0
0
1
0
1
0
1
0
1
Scaling Mode
Scaling Mode
Scale down
Scale down
Description
No scaling
No scaling
Reserved
Reserved
Scale up
Scale up
Central Processor Unit (CPU) Registers
U = (Bit 47 XOR Bit
46)
U = (Bit 48 XOR Bit
47)
U = (Bit 46 XOR Bit
45)
U undefined
Integer Portion
Integer Portion
Bits 55–47
Bits 55–48
Undefined
Bits 5–46
4-11