DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 127

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Note:
6.7.6 Transmit Data Registers (TXH:TXM:TXL)
The host processor views the transmit byte registers as three 8-bit write-only registers. These
registers are the transmit high register (TXH), the transmit middle register (TXM), and the
transmit low register (TXL). These registers send data to the high, middle, and low bytes,
respectively, of the HRX register and are selected by the external host address inputs, HA[2–0],
during a host processor write operation.
If ICR[HLEND] is set, the TXH register is located at address $7, the TXM register at $6, and the
TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH register is located at address
$5, the TXM register at $6, and the TXL register at $7.
Data can be written into the transmit byte registers when the ISR transmit data register empty
(TXDE) bit is set. The host processor can program the ICR[TREQ] bit to assert the external
HREQ/HTRQ signal when ISR[TXDE] is set. This informs the host processor that the transmit
byte registers are empty. Writing to the data register at host address $7 clears the ISR[TXDE] bit.
The contents of the transmit byte registers are transferred as 24-bit data to the HRX register when
both ISR[TXDE] and HSR[HRDF] are cleared. This transfer operation sets HSR[TXDE] and
HSR[HRDF]. The external host should never write to the TXH:TXM:TXL registers if the
ISR[TXDE] bit is cleared.
Note:
6.7.7 Host-Side Registers After Reset
Table 6-18 shows the result of the four kinds of reset on bits in each of the HI08 registers seen by
the host processor. To cause a hardware reset, assert the
execute the RESET instruction. To reset the HEN bit individually, clear the HPCR[HEN] bit. To
cause a stop reset, execute the STOP instruction.
Freescale Semiconductor
Register
Name
CVR
ICR
The external host should never read the RXH:RXM:RXL registers if the ISR[RXDF]
bit is cleared.
When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of those status
bits within the next two cycles, the bit will not reflect its current status. For details, see
Section 5.4.1, Polling, on page 1-3.
Register
HV[0–6]
All bits
Data
HC
Table 6-18. Host-Side Registers After Reset
DSP56303 User’s Manual, Rev. 2
Reset
HW
$32
0
0
Reset
SW
$32
0
0
RESET
Individual Reset
Reset Type
—
—
0
signal. To cause a software reset,
Host Programmer Model
STOP
—
—
0
6-27