DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 182

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Communication Interface (SCI)
8-14
Number
2–0
Bit
4
3
SSFTD
Name
WDS
SBK
Bit
Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Reset
Value
0
0
0
Send Break
A break is an all-zero word frame—a start bit 0, characters of all zeros (including any
parity), and a stop bit 0 (that is, ten or eleven zeros, depending on the mode selected). If
SBK is set and then cleared, the transmitter finishes transmitting the current frame,
sends 10 or 11 0s, and reverts to idle or sending data. If SBK remains set, the transmitter
continually sends whole frames of 0s (10 or 11 bits with no stop bit). At the end of the
break code, the transmitter sends at least one high (set) bit before transmitting any data
to guarantee recognition of a valid start bit. Break can signal an unusual condition,
message, and so on, by forcing a frame error; the frame error is caused by a missing
stop bit.
SCI Shift Direction
Determines the order in which the SCI data shift registers shift data in or out: MSB first
when set, LSB first when cleared. The parity and data type bits do not change their
position in the frame, and they remain adjacent to the stop bit.
Word Select
Select the format of transmitted and received data. Asynchronous modes are compatible
with most UART-type serial devices, and they support standard RS-232 communication
links. Multidrop Asynchronous mode is compatible with the MC68681 DUART, the
M68HC11 SCI interface, and the Intel 8051 serial interface. Synchronous data mode is
essentially a high-speed shift register for I/O expansion and stream-mode channel
interfaces. You can synchronize data by using a gated transmit and receive clock
compatible with the Intel 8051 serial interface mode 0. When odd parity is selected, the
transmitter counts the number of ones in the data word. If the total is not an odd number,
the parity bit is set, thus producing an odd number. If the receiver counts an even number
of ones, an error in transmission has occurred. When even parity is selected, an even
number must result from the calculation performed at both ends of the line, or an error in
transmission has occurred.
WDS2
0
0
0
1
1
1
1
0
DSP56303 User’s Manual, Rev. 2
WDS1
0
0
1
1
0
0
1
1
WDS0
0
1
0
1
0
1
0
1
Mode
0
1
2
3
4
5
6
7
Description
8-Bit Synchronous Data (shift register mode)
Reserved
10-Bit Asynchronous (1 start, 8 data, 1 stop)
Reserved
11-Bit Asynchronous
(1 start, 8 data, 1 even parity, 1 stop)
11-Bit Asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)
11-Bit Multidrop Asynchronous
(1 start, 8 data, 1 data type, 1 stop)
Reserved
Word Formats
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