DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 33

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

2.7 Host Interface (HI08)
The HI08 provides a fast, parallel data-to-8-bit port that can directly connect to the host bus. The
HI08 supports a variety of standard buses and can directly connect to a number of
industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.
2.7.1 Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are written
by another asynchronous system. This is a common problem when two asynchronous systems are
connected (as they are in the Host port). The considerations for proper operation are discussed in
Table 2-10.
2.7.2 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as
determined by the 16 bits in the HI08 Port Control Register (HPCR). Refer to the Chapter 6,
Host Interface (HI08), for detailed descriptions of HI08 configuration registers.
Freescale Semiconductor
Asynchronous read of receive
byte registers
Asynchronous write to
transmit byte registers
Asynchronous write to host
vector
MODD/IRQD
Signal Name
Action
Input
Type
Table 2-9. Interrupt and Mode Control (Continued)
Input
State During
To assure that the data in the receive byte registers is valid when you are reading the r
Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL),
use interrupts or poll the Receive Register Data Full (RXDF) flag that indicates data is
available.
To ensure that the transmit byte registers transfer valid data to the Host Receive (HRX)
register, do not write to the Transmit register High (TXH), Transmit register Middle (TXM), or
Transmit register Low (TXL) registers unless the Transmit register Data Empty (TXDE) bit is
set indicating that the transmit byte registers are empty.
To ensure that the DSP interrupt control logic receives a stable vector, change the Host
Vector (HV) register only when the Host Command bit (HC) is clear.
Table 2-10. Host Port Usage Considerations
Reset
DSP56303 User’s Manual, Rev. 2
Mode Select D/External Interrupt Request D
Selects the initial chip operating mode during hardware reset and becomes
a level-sensitive or negative-edge-triggered, maskable interrupt request
input during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into OMR
when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQD is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQD to exit the Wait state.
MODD/IRQD can tolerate 5 V.
Description
Signal Description
Host Interface (HI08)
2-9