DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 78

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Core Configuration
4.5 PLL Control Register (PCTL)
The bootstrap program must initialize the system Phase-Lock Loop (PLL) circuit by configuring
the PLL Control Register (PCTL). The PCTL is an X-I/O mapped, read/write register that directs
the internal PLL operation. (See Figure 4-5.)
Table 4-7 defines the DSP56303 PCTL bits. Changing the following bits may cause the PLL to
lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF.
4-20
Bit Number
MF11
PD3
23
11
23–20
19
18
17
16
Priority
Lowest
MF10
PD2
22
10
Bit Name
PD[3–0]
PSTP
XTLD
COD
PEN
Table 4-6. Interrupt Source Priorities Within an IPL (Continued)
MF9
PD1
21
9
Table 4-7. PLL Control Register (PCTL) Bit Definitions
Reset Value
Set to PINIT
input value
MF8
PD0
TIMER0 compare interrupt
TIMER1 overflow interrupt
TIMER1 compare interrupt
TIMER2 overflow interrupt
TIMER2 compare interrupt
Figure 4-5. PLL Control Register (PCTL)
20
8
0
0
0
0
COD
MF7
DSP56303 User’s Manual, Rev. 2
19
7
Predivider Factor
Define the predivision factor (PDF) to be applied to the PLL input frequency.
The PD[3–0] bits are cleared during DSP56303 hardware reset, which
corresponds to a PDF of one.
Clock Output Disable
Controls the output buffer of the clock at the CLKOUT pin. When COD is set,
the CLKOUT output is pulled high. When COD is cleared, the CLKOUT pin
provides a 50 percent duty cycle clock.
PLL Enable
Enables PLL operation.
PLL Stop State
Controls PLL and internal crystal oscillator behavior during the stop processing
state.
XTAL Disable
Controls the internal crystal oscillator XTAL output. The XTLD bit is cleared
during DSP56303 hardware reset, so the XTAL output signal is active,
permitting normal operation of the crystal oscillator.
PEN
MF6
18
6
PSTP
MF5
17
5
Interrupt Source
XTLD
MF4
16
4
Description
XTLR
MF3
15
3
DF2
MF2
14
2
Freescale Semiconductor
DF1
MF1
13
1
DF0
MF0
12
0