DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 68

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Core Configuration
4-10
Bit Number
11–10
9–8
12
7
6
Bit Name
S[1–0]
I[1–0]
S
L
Table 4-2. Status Register Bit Definitions (Continued)
Reset Value
11
0
0
0
0
DSP56303 User’s Manual, Rev. 2
Reserved. Write to 0 for future compatibility.
Scaling Mode
Specify the scaling to be performed in the Data ALU shifter/limiter and the
rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling mode
affects data read from the A or B accumulator registers out to the X-data bus
(XDB) and Y-data bus (YDB). Different scaling modes can be used with the
same program code to allow dynamic scaling. One application of dynamic
scaling is to facilitate block floating-point arithmetic. The scaling mode also
affects the MAC rounding position to maintain proper rounding when different
portions of the accumulator registers are read out to the XDB and YDB.
Scaling mode bits are cleared at the start of a long Interrupt Service Routine
and during a hardware reset.
Interrupt Mask
Reflect the current Interrupt Priority Level (IPL) of the processor and indicate
the IPL needed for an interrupt source to interrupt the processor. The current
IPL of the processor can be changed under software control. The interrupt
mask bits are set during hardware reset, but not during software reset.
Lowest
Highest
Scaling
Set when a result moves from accumulator A or B to the XDB or YDB buses
(during an accumulator to memory or accumulator to register move) and
remains set until explicitly cleared; that is, the S bit is a sticky bit. The logical
equations of this bit are dependent on the Scaling mode. The scaling bit is set
if the absolute value in the accumulator, before scaling, is > 0.25 or < 0.75.
Limit
Set if the overflow bit is set or if the data shifter/limiter circuits perform a
limiting operation. In Arithmetic Saturation mode, the L bit is also set when an
arithmetic saturation occurs in the Data ALU result; otherwise, it is not
affected. The L bit is cleared only by a processor reset or by an instruction that
specifically clears it (that is, a sticky bit); this allows the L bit to be used as a
latching overflow bit. The L bit is affected by data movement operations that
read the A or B accumulator registers.
Priority
S1
0
0
1
1
S0
I1
0
1
0
1
0
0
1
1
Scale down
No scaling
Reserved
Scale up
Scaling
Mode
I0
0
1
0
1
Description
IPL 0, 1, 2, 3
IPL 1, 2, 3
IPL 2, 3
IPL 3
Rounding Bit
Exceptions
Permitted
23
24
22
—
Freescale Semiconductor
None
IPL 0
IPL 0, 1
IPL 0, 1, 2
Exceptions Masked
S = (A46 XOR A45)
OR (B46 XOR B45)
S = (A47 XOR A46)
OR (B47 XOR B46)
S = (A45 XOR A44)
OR (B45 XOR B44)
OR S (previous)
OR S (previous)
OR S (previous)
S undefined
SEquation