DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 43

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

JTAG/OnCE Interface
Table 2-16. JTAG/OnCE Interface (Continued)
State During
Signal Name
Type
Signal Description
Reset
DE
Input/Output
Input
Debug Event
Provides
a way to enter Debug mode from an external command
controller (as input) or to acknowledge that the chip has entered
DE
Debug mode (as output). When asserted as an input,
causes
the DSP56300 core to finish the current instruction, save the
instruction pipeline information, enter Debug mode, and wait for
commands from the debug serial input line. When a debug request
DE
or a breakpoint condition cause the chip to enter Debug mode
is
DE
asserted as an output for three clock cycles.
has an internal
pull-up resistor.
DE
is not a standard part of the JTAG Test Access Port (TAP)
Controller. It connects to the OnCE module to initiate Debug mode
directly or to provide a direct external indication that the chip has
entered the Debug mode. All other interface with the OnCE module
must occur through the JTAG port. This input is 5 V tolerant.
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor
2-19