DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 219

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
Bit Number
Mode
0
1
2
3
4
5
2
1
0
GPIO signal on the TIO signal
read directly.
Counter is incremented on the
rising edge of the signal from
the TIO signal.
Counter is incremented on the
rising edge of the signal from
the TIO signal.
Counter is incremented on the
rising edge of the signal from
the TIO signal.
Width of the high input pulse is
measured.
Period is measured between
the rising edges of the input
signal.
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Name
TCIE
TOIE
TE
INV = 0
TIO Programmed as Input
Reset Value
Table 9-4. Inverter (INV) Bit Operation
0
0
0
GPIO signal on the TIO signal
inverted.
Counter is incremented on
the falling edge of the signal
from the TIO signal.
Counter is incremented on
the falling edge of the signal
from the TIO signal.
Counter is incremented on
the falling edge of the signal
from the TIO signal.
Width of the low input pulse is
measured.
Period is measured between
the falling edges of the input
signal.
DSP56303 User’s Manual, Rev. 2
Timer Compare Interrupt Enable
Enables/disables the timer compare interrupts. When set, TCIE enables the
compare interrupts. In the timer, pulse width modulation (PWM), or watchdog
modes, a compare interrupt is generated after the counter value matches the
value of the TCPR. The counter starts counting up from the number loaded
from the TLR and if the TCPR value is M, an interrupt occurs after (M – N + 1)
events, where N is the value of TLR. When cleared, the TCSR[TCIE] bit
disables the compare interrupts.
Timer Overflow Interrupt Enable
Enables timer overflow interrupts. When set, TOIE enables overflow interrupt
generation. The timer counter can hold a maximum value of $FFFFFF. When
the counter value is at the maximum value and a new event causes the
counter to be incremented to $000000, the timer generates an overflow
interrupt. When cleared, the TOIE bit disables overflow interrupt generation.
Timer Enable
Enables/disables the timer. When set, TE enables the timer and clears the
timer counter. The counter starts counting according to the mode selected by
the timer control (TC[3–0]) bit values. When clear, TE bit disables the timer.
Note:
INV = 1
When all three timers are disabled and the signals are not in GPIO
mode, all three TIO signals are tri-stated. To prevent undesired
spikes on the TIO signals when you switch from tri-state into active
state, these signals should be tied to the high or low signal state by
pull-up or pull-down resistors.
Bit written to GPIO
put on TIO signal
directly.
Initial output put on
TIO signal directly.
Description
Triple Timer Module Programming Model
INV = 0
TIO Programmed as Output
—
—
—
—
Bit written to GPIO
inverted and put on TIO
signal.
Initial output inverted
and put on TIO signal.
INV = 1
—
—
—
—
9-27