MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 211
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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7.3.2.11
7.3.2.12
Freescale Semiconductor
Module Base + 0x002D
Module Base + 0x002E
Starting address location affected by INITRG register setting.
EXTCMP
PAGSEL
Reset
Reset
Field
7:6
5:0
W
W
R
R
Bit 15
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
11.
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively.)
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
Debug Comparator B Extended Register (DBGCBX)
Debug Comparator B Register (DBGCB)
15
0
0
7
Table 7-11
PAGSEL
Figure 7-19. Debug Comparator B Extended Register (DBGCBX)
Figure 7-20. Debug Comparator B Register High (DBGCBH)
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see
Bit 14
14
0
0
6
Table 7-22. DBGCBX Field Descriptions
Bit 13
13
0
0
5
MC9S12Q128
Bit 12
Rev 1.09
12
0
0
4
Description
Bit 11
11
0
0
3
Chapter 7 Debug Module (DBGV1) Block Description
EXTCMP
Bit 10
10
0
0
2
Bit 9
0
0
1
9
Table
Bit 8
Table 7-
0
0
0
8
7-20.
211
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