MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 81

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MC9S12Q

Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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2.3.2.1.2
Read: Anytime.
Write: Never, writes to this register have no effect.
2.3.2.1.3
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x0001
Module Base + 0x0002
DDRT[7:0]
PTIT[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
DDRT7
PTIT7
Port T Input Register — This register always reads back the status of the associated pins. This can also be
used to detect overload or short circuit conditions on output pins.
Data Direction Port T — This register configures each port T pin as either input or output.
The standard TIM / PWM modules forces the I/O state to be an output for each standard TIM / PWM module port
associated with an enabled output compare. In these cases the data direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer input capture always monitors the state of the pin.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTT
0
7
7
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
or PTIT registers, when changing the DDRT register.
= Unimplemented or Reserved
DDRT6
PTIT6
0
6
6
Figure 2-5. Port T Data Direction Register (DDRT)
Figure 2-4. Port T Input Register (PTIT)
Table 2-5. DDRT Field Descriptions
DDRT5
Table 2-4. PTIT Field Descriptions
PTIT5
0
5
5
MC9S12Q128
DDRT4
PTIT4
Rev 1.09
0
4
4
Description
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
DDRT3
PTIT3
0
3
3
DDRT2
PTIT2
0
2
2
DDRT1
PTIT1
0
1
1
DDRT0
PTIT0
0
0
0
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