MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 79
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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2.3.2
Table 2-2
level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1. Applicable only on ports P and J.
Freescale Semiconductor
DDR
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
summarizes the effect on the various configuration bits — data direction (DDR), input/output
IO
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Register Descriptions
All bits of all registers in this module are completely synchronous to internal
clocks during a register read.
RDR
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
PE
X
X
X
X
X
X
X
X
0
1
1
0
0
1
1
PS
X
0
1
0
1
0
1
X
X
X
X
0
1
0
1
Table 2-2. Pin Configuration Summary
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(1)
MC9S12Q128
Output, reduced drive to 0
Output, reduced drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Rev 1.09
Output, full drive to 0
Output, full drive to 1
Output, full drive to 0
Output, full drive to 1
NOTE
Function
Chapter 2 Port Integration Module (PIM9C32) Block Description
Input
Input
Input
Input
Input
Input
Input
Pull Device
Pull down
Pull down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull up
Pull up
Falling edge
Rising edge
Falling edge
Falling edge
Rising edge
Falling edge
Rising edge
rising edge
Interrupt
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
79
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