MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 411
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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14.2.2
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
14.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when its configured as a master and its used as an input to receive the slave select
signal when the SPI is configured as slave.
14.2.4
This pin is used to output the clock with respect to which the SPI transfers data or receive clock in case of
slave.
14.3
This section provides a detailed description of address space and registers used by the SPI.
The memory map for the SPIV3 is given below in
sum of a base address and an address offset. The base address is defined at the SoC level and the address
offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved
bits have no effect.
14.3.1
Freescale Semiconductor
1. Certain bits are non-writable.
2. Writes to this register are ignored.
3. Reading from this register returns all zeros.
Memory Map and Register Definition
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
MISO — Master In/Slave Out Pin
SCK — Serial Clock Pin
Module Memory Map
SS — Slave Select Pin
SPI Control Register 1 (SPICR1)
SPI Control Register 2 (SPICR2)
SPI Baud Rate Register (SPIBR)
SPI Status Register (SPISR)
Reserved
SPI Data Register (SPIDR)
Reserved
Reserved
Table 14-1. SPIV3 Memory Map
MC9S12Q128
Rev 1.09
Table
Use
Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
14-1. The address listed for each register is the
Access
R/W
—
R/W
—
—
R/W
R/W
R
2,(3)
(2)
2,3
2,3
(1)
1
411
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