MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 352
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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Chapter 12 Pulse-Width Modulator (PWM8B4C) Block Description
Read: anytime
Write: anytime
352
Module Base + 0x0000
PWME3
PWME2
PWME1
PWME0
Reset
Field
3
2
1
0
W
R
Pulse Width Channel 3 Enable
0 Pulse width channel 3 is disabled.
1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when
Pulse Width Channel 2 Enable
0 Pulse width channel 2 is disabled.
1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when
Pulse Width Channel 1 Enable
0 Pulse width channel 1 is disabled.
1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when
Pulse Width Channel 0 Enable
0 Pulse width channel 0 is disabled.
1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when
0
0
7
its clock source begins its next cycle.
its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line 0 is disabled.
= Unimplemented or Reserved
0
0
6
Figure 12-3. PWM Enable Register (PWME)
Table 12-1. PWME Field Descriptions
0
5
MC9S12Q128
Rev 1.09
0
4
Description
PWME3
0
3
PWME2
0
2
PWME1
Freescale Semiconductor
0
1
PWME0
0
0
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